CSCE 434/834: VLSI Design, Fall 2010

Department of Computer Science and Engineering

University of Nebraska-Lincoln

11:30-12:20 PM, M-W-F, Avery Hall, Room 112

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Syllabus

Web Handin

UNL BlackBoard

Web Links

News & Announcements

Instructor:  Sharad C. Seth, Avery Hall, Room 359

Phone: 472-5003
Email: seth at cse dot unl dot edu
Office Hours:  TBA (send email to see me, otherwise)

Required Text Book: CMOS VLSI Design: A Circuits and Systems Perspective, 4/E, Neil Weste and David Harris, ISBN‐10: 0321547748 ISBN‐13: 9780321547743, Publisher: Addison‐Wesley: 2011 Format: Cloth; 864 pp. (Textbook author David Harris' home page and to his Introduction to CMOS VLSI Design course web page). Note that the new edition thoroughly updates all the material in 3E which was published in 2004. In terms of the topics coverage, here is my comparison of the two editions. Errata sheets for the two editions can be found at the David Harris' web supplements page. I am beginning to compile the errors in 4/E as I discover them and recording them here. If you find any errors, do let me know and I will add them to this list.

Course Announcement:

Lecture Schedule

Week of	Monday		Wednesday		Friday
	Topics	Assignment	Topics	Assignment	Topics	Assignment
8/23	First-day (Syllabus), Course Introduction	Read The Landscape of Parallel Computing Research: A View from Berkeley Read Sections 1.1-1.4 of the textbook	Introduction-1 (contd.)		Introduction-1 (contd.) Introduction-2 CMOS gates and sequential logic	HW 1 out
8/30	Introduction-2 (contd.)		Introduction-3 Physical design and Fabrication		Getting Started with Cadence at UNL-CSE Introduction-3 (contd.)	Lab 1 out (due in 2 weeks)
9/6	LABOR DAY - NO CLASS		Introduction-3 (Layout and Fabrication)	HW 2 out	MOSIS (3-metal, 1-poly) submicron design uules (In-class exercise), Layout with single vs. multiple lines of diffusion, Introduction-4 (System-level design: MIPS architecture)
9/13	Design at the system, circuit, and physical levels: Introduction-4 (contd.) and Introduction-5		Physical design: Introduction-5 (contd.) and  Transistor Theory-6		Getting Started with Cadence at UNL-CSE (updated for Lab 2) Transistor Theory-6 (contd.) Non-ideal Transistors-7 (review most of it on your own, I will talk about leakage current, and process corners.	Lab 2 out (due in 1 week)
9/20	Non-ideal Transistor-7 (cond.) DC-Response-8		DC-Response-8 (contd.) Transient Response-9		No class due to my involvement in Hall of Computing activities today
9/27	Linear delay model and logical effort-10			HW-3 out	Return and discuss HW 2 (A good solution to Problem 2), Intro. to low-power design-11	Lab 3 (delayed until next week)
10/4	Low-power design (contd)		Low-power design (contd.)		Brief Q&A on HW 3, Introduction to Lab 3, Low-power design (contd.)	Lab 3 out (tentatively, due in 1 week), changes (also see Getting Started ...)
10/11	Iterative Solution for Sizing, Sizing for Minimum Delay (Excel sheet for Example  4.15 of the text and the full adder)		Power dependence on switching factor and capacitance, Gate sizing for power minimization under delay constraints (Excel sheet for the full-adder example)		Power overheads from the author (Review, particularly, how to reduce static power consumption) Combinational Logic Design (static CMOS and other circuit families)	Lab 4 out, changes (due in one week) HW 4 out (due Oct 25)
10/18	FALL BREAK
10/25			Sequential Circuits
11/1	Sequential Circuits (contd)	HW 5 out (due 11/10)			Adders
11/8	Other datapath circuits		Memory arrays
11/15	Memory arrays (CAMs), Testing and Design for Testability		Testing and Design for Testability	HW 6 out (due 11/29)	Testing and Design for Testability
11/22			THANKSGIVING BREAK		THANKSGIVING BREAK
11/29	Clock generation and distribution		Physical Design Automation		Physical Design Automation
12/6	NO CLASS		NO CLASS		Project Presentation
12/14	10-12 AM: Project Presentations (Reports due today)

Web Links

• Textbook (CMOS VLSI Design, 4e) Web Supplements: The site has Web enhanced supplements to the textbook material, author's lecture slides, textbook figures, errata, Labs from author's course, and Spice & Verilog code from examples in the textbook)

• Textbook author David Money Harris' Home Page: Includes many good links related to this course.

• Cadence design software related links:
• Cadence Design Systems
• NCSU CDK wiki page (includes  tutorials on Cadence tools, among others)
• OSU Cadence Central page (has many useful links related to Cadence-based design and MOSIS fabrication)
• Master's thesis by James R. Copus describing the OSU digital cell library
• Tutorials: from North Carolina State University, Worcester Polytechinc, and  Rensselaer Polytechnic Institute
• University of Utah Cadence University Program page
• San Jose State University IC Design Group page
• Design of a cell library for asynchronous microengines by G. Gulati and E. Brunvand from University of Utah (GLSVLSI'05)
• Fedora Electronic Lab: "Fedora's Electronic Laboratory, an opensource hardware design and simulation platform, is dedicated to support the innovation and development brought by opensource Electronic Design Automation (EDA) community."


• Electronic design automation: Wikipedia entry

• IWLS Benchmarks: Various public-domain benchmarks collected for the International Workshop for Logic Synthesis. The benchmarks are described at this presentation at the IWLS2005 workshop.

• Class web pages for Introductory VLSI courses
• Havery-Mudd
• Univeristy of Utah

• On chip fabrication
• Intel: "From Sand to Silicon Making of a Chip" video, 2':11" describes, in brief, the fabrication process for the 45 nm technology in video and 32 nm technology in slides.
• Intel Higher Education Curriculum Forum: An Interdisciplinary Model for Education in Microelectronic Fabrication.
• Silicon Run Productions: Semiconductor Technology Videos (I have copies of Silicon Run I and II available for loan)
• The MOSIS Service available to us for free fabrication of class project. Go here for details on MOSIS Educational Program (MEP) Accounts
• The Stanford Nanofabrication Facility

• Interesting articles:
• "The Landscape of Parallel Computing Research: A View from Berkeley", Technical Report No. UCB/EECS-2006-183, December 18, 2006.
• D. Patterson, "The trouble with multi-core", IEEE Spectrum, July 2010.
• Richard P. Feynman, "The computing machines in the future", address presented at Gakushuin University (Tokyo) on August 9, 1985. 
• Richard P. Feynman, "There is pleny of room at the bottom", talk given on Dec. 29, 1959 to the American Physical Society on what possibilities of devices exist at the nanoscale.

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