| Lesson | Date | Topic | Reading | Assigned | Due |
|---|---|---|---|---|---|
| L1 | Jan 13 | Intro, Entity and architecture, Digital Systems Design | 1.1-1.7 | HW #1 | BOC L2 |
| L2 | Jan 15 | Digital Systems, hierarchical design, testbench | 2.1, 2.2.1, 2.2.2 | HW #2 | BOC L3 |
| L3 | Jan 17 | Combinational elements, unsigned, constraints file, synthesis | 3.5.4, 4.2.3, 4.3.1 | HW #3 | BOC L4 |
| L4 | Jan 22 | Sequential elements | 5.1, 5.2, 5.7, 5.8 | HW #4 | BOC L5 |
| L5 | Jan 24 | Combinations of elements, lab intro | 7.2 | HW #5 | BOC L6 |
| L6 | Jan 27 | Lab1 - VGA Synchronization | |||
| L7 | Jan 29 | Lab1 - VGA Synchronization | Gate Check 1 | BOC L7 | |
| L8 | Jan 31 | Lab1 - VGA Synchronization | Gate Check 2 | BOC L8 | |
| L9 | Feb 3 | Lab1 - VGA Synchronization | Lab1 Functionality | COB L9 | |
| L10 | Feb 5 | Finite State Machines | 10.2.1, 10.3.2, 10.4, 10.6.1 | Lab1 Write-up HW #6 |
COB L10 BOC L11 |
| L11 | Feb 7 | Datapath and Control | 11.1, 11.2, 14.4.2 | HW #7 | BOC L12 |
| L12 | Feb 10 | Datapath and Control | 11.5 | HW #8 | BOC L13 |
| L13 | Feb 12 | Datapath and Control | |||
| L14 | Feb 14 | Lab2 - Data acquisition, storage and display | Gate Check 1 | COB L14 | |
| L15 | Feb 17 | Exam #1 | |||
| L16 | Feb 19 | Lab2 - Data acquisition, storage and display | Gate Check 2 | BOC L16 | |
| L17 | Feb 21 | Lab2 - Data acquisition, storage and display | Lab2 Functionality | COB L17 | |
| L18 | Feb 24 | Soft CPU | Lab2 Write-up HW #9 |
COB L18 BOC L19 | |
| L19 | Feb 26 | Soft CPU | HW #10 | BOC L20 | |
| L20 | Feb 28 | Soft CPU | HW #11 | BOC L21 | |
| L21 | Mar 2 | Lab3 - O'scope control | Final Project Ideas |
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| L22 | Mar 4 | Lab3 - O'scope control | Gate Check 1 | BOC L22 | |
| L23 | Mar 6 | Lab3 - O'scope control | Gate Check 2 | BOC L23 | |
| L24 | Mar 9 | Lab3 - O'scope control | |||
| L25 | Mar 11 | Direct Digital Synthesis | Lab3 Functionality | COB L25 | |
| L26 | Mar 13 | Direct Digital Synthesis | Lab3 Write-up Final Project Proposal |
COB L26 BOC L27 | |
| L27 | Mar 16 | Digital Low Pass Filter | Revised Final Project Proposal | BOC L28 | |
| L28 | Mar 18 | Digital Low Pass Filter | HW #12 | BOC L29 | |
| L29 | Mar 20 | Lab4 - Function generator | Gate Check #1 | EOC L29 | |
| L30 | Mar 30 | Lab4 - Function generator | Gate Check #2 | EOC L30 | |
| L31 | Apr 1 | Lab4 - Function generator | Lab4 Functionality | COB L31 | |
| L32 | Apr 3 | Asynchronous Design FPGA fabric |
Lab4 Write-up | COB L32 | |
| L33 | Apr 6 | ||||
| L34 | Apr 8 | Lab5 - Final Project Milestone #1 |
Final Project Plan | BOC L34 | |
| L35 | Apr 10 | Lab5 - Final Project Milestone #1 |
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| L36 | Apr 13 | Exam #2 Communication Skills (writing) |
Milestone#1 | BOC L36 | |
| L37 | Apr 15 | Lab5 - Final Project Milestone #2 |
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| L38 | Apr 17 | Lab5 - Final Project Milestone #2 |
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| L39 | Apr 20 | Communication Skills (speaking) | Milestone#2 | BOC L39 | |
| L40 | Apr 22 | Lab5 - Final Project Final push |
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| L41 | Apr 24 | Lab5 - Final Project Final push |
Project Write-up | COB L41 | |
| L42 | Apr 27 | Final Presentations | Final Presentation | BOC L42 | |
| L43 | Apr 29 | Final Presentations | Final Presentation | BOC L42 |