CSCE 436

Homework #1

Guidelines

  1. [1.2] Volume of sale (i.e., the number of parts sold) is a factor when determining which device technology is to be used. Assume that a system can be implemented by FPGA, gate array or standard-cell technology. The per-part cost is $15, $3, and $1 for FPGA, gate array, and standard cell respectively. Gate-array and standard-cell technologies also involve a one-time mask generation cost of $20,000 and $100,000 respectively. Assume the number of parts sold is N. Derive the equation of per-unit cost for the three technologies.
    1. Assume the number of parts sold is N. Derive the equation of per-unit cost for the three technologies.
    2. Plot the equations with N as the x-axis similar to unit cost diagram from Lecture 1.
    3. Determine the range of N for which FPGA technology has the minimal per-unit cost.
    4. Determine the range of N for which gate-array technology has the minimal per-unit cost.
    5. Determine the range of N for which standard-cell technology has the minimal per-unit cost.
  2. [1.3] What is the view (behavioral, structural, or physical) of the following illustration?


  3. [1.4] What is abstraction? Why is it important for digital system design?
  4. [1.5] What is the difference between testing and verification?
  5. Install and test Xilinx Vivado (Version 2019.1): Vivado Installation Instructions (PPT with project start) Vivado Installation Instructions (PDF)
  6. Design a digital system with four bits of inputs I3 I2 I1 I0 and two bits of outputs O1 O0. At least one of the inputs is always equal to 1. The output encodes the index of the most significant 1 in the input. For example, if I3 I2 I1 I0 = 0101, then the index of the most significant 1 is 2, hence O1 O0 = 10. Hint, you will need a don't care somewhere. Turn in....
    1. Complete truth table.

    2. Two 4-variable kmaps.

    3. Minimal SOP expressions for O1 and O0
      O0 (I3,I2,I1,I0) =
      O1 (I3,I2,I1,I0) =
    4. VHDL code for the circuit (attached to Canvas quiz and pushed to BitBucket). Make sure that you have a proper file header. Testbench is not required for this homework
  7. Please sign up for a BitBucket account if you don't already have one using your unl.edu e-mail. Create a Private Repository named "CSCE_436_YourLastName" and give me (jfalkinburg2@unl.edu) read/write access. You will also need to create an issue tracker and wiki for the Repo. Note: It is very important that you put this repository in a location on your computer that doesn't have any spaces in the path.