| Lesson | Date | Topic | Reading | Assigned | Due |
|---|---|---|---|---|---|
| L1 | Jan 12 | Course Intro, entity and architecture, digital systems design | 1.1-1.7 | HW #1 | BOC L2 |
| L2 | Jan 14 | Digital Systems, hierarchical design, testbenches | 2.1, 2.2.1, 2.2.2 | HW #2 | BOC L3 |
| L3 | Jan 16 | Combinational elements, unsigned, constraints file, synthesis | 3.5.4, 4.2.3, 4.3.1 | HW #3 | BOC L4 |
| Break | Jan 19 | Martin Luther King Day - no class | no class | ||
| L4 | Jan 21 | VHDL Sequential elements - Mod 10 Counter | 5.1, 5.2, 5.7, 5.8 | HW #4 | BOC L5 |
| L5 | Jan 23 | Combinations of elements, gated & non-gated, lab intro | 7.2 | HW #5 | BOC L6 |
| L6 | Jan 26 | Lab1 - VGA Synchronization | |||
| L7 | Jan 28 | Lab1 - VGA Synchronization | Gate Check 1 | BOC L7 | |
| L8 | Jan 30 | Lab1 - VGA Synchronization | Gate Check 2 | BOC L8 | |
| L9 | Feb 2 | Lab1 - VGA Synchronization | Lab1 Functionality | COB L9 | |
| L10 | Feb 4 | Finite State Machines, FSM timing, The DAISY system | 10.2.1, 10.3.2, 10.4, 10.6.1 | Lab1 Write-up HW #6 |
COB L10 BOC L11 |
| L11 | Feb 6 | Datapath and Control: generics, design, BBB, find Min | 11.1, 11.2, 14.4.2 | HW #7 | BOC L12 |
| L12 | Feb 9 | Datapath and Control - timing, Keyboard example | 11.5 | HW #8 | BOC L13 |
| L13 | Feb 11 | Datapath and Control: BRAM Macro, 2-Line Handshake | |||
| L14 | Feb 13 | Lab2 - Data acquisition, storage and display | Gate Check 1 | COB L14 | |
| L15 | Feb 16 | Lab2 - Data acquisition, storage and display | |||
| L16 | Feb 18 | Lab2 - Data acquisition, storage and display | Gate Check 2 | BOC L16 | |
| L17 | Feb 20 | Lab2 - Data acquisition, storage and display | Lab2 Functionality | COB L17 | |
| L18 | Feb 23 | Soft CPU - "MicroBlaze" | Lab2 Write-up HW #9 |
COB L18 BOC L19 | |
| L19 | Feb 25 | Soft CPU - "MicroBlaze" + Custom IP | HW #10 | BOC L20 | |
| L20 | Feb 27 | Soft CPU - "MicroBlaze" + Custom IP w/ Interrupts | HW #11 | BOC L21 | |
| L21 | Mar 2 | Lab3 - O'scope control | Final Project Ideas |
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| L22 | Mar 4 | Lab3 - O'scope control | Gate Check 1 | BOC L22 | |
| L23 | Mar 6 | Lab3 - O'scope control | Gate Check 2 | BOC L23 | |
| L24 | Mar 9 | Lab3 - O'scope control | |||
| L25 | Mar 11 | Direct Digital Synthesis: fixed point numbers & phase inc | Lab3 Functionality | COB L25 | |
| L26 | Mar 13 | Direct Digital Synthesis: Look-Up Table (LUT) | Lab3 Write-up Final Project Proposal - Draft |
COB L26 BOC L27 | |
| Break | Mar 16-20 | Spring Break - no class | no class | ||
| L27 | Mar 23 | Digital Low Pass Filter: Filtering Design | BOC L28 | ||
| L28 | Mar 25 | Digital Low Pass Filter: Digital Filter in Theory | Revised Final Project Proposal HW #12 |
BOC L29 BOC L29 | |
| L29 | Mar 27 | Lab4 - Function generator | Gate Check #1 | EOC L29 | |
| L30 | Mar 30 | Lab4 - Function generator | Gate Check #2 | EOC L30 | |
| L31 | Apr 1 | Lab4 - Function generator | Lab4 Functionality | COB L31 | |
| L32 | Apr 3 | Asynchronous Design FPGA fabric |
Lab4 Write-up Officially begin Lab5 - Final Project |
COB L32 | |
| L33 | Apr 6 | Lab5 - Final Project Milestone #1 |
Final Project Plan | BOC L33 | |
| L34 | Apr 8 | Lab5 - Final Project Milestone #1 |
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| L35 | Apr 10 | Lab5 - Final Project Milestone #1 |
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| L36 | Apr 13 | Communication Skills (writing) Lab5 - Final Project - Milestone #2 |
Milestone#1 | BOC L36 | |
| L37 | Apr 15 | Lab5 - Final Project Milestone #2 |
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| L38 | Apr 17 | Lab5 - Final Project Milestone #2 |
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| L39 | Apr 20 | Communication Skills (speaking) Lab5 - Final Project - Final push |
Milestone#2 | BOC L39 | |
| L40 | Apr 22 | Lab5 - Final Project Final push |
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| L41 | Apr 24 | Lab5 - Final Project Final push Senior Design Showcase - no class |
no class | ||
| L42 | Apr 27 | Final Presentations | Project Functionality and Presentations | BOC L42 | |
| L43 | Apr 29 | Final Presentations | Final Presentation | BOC L42 | |
| L44 | May 1 | Final Presentations | Project Write-up | EOC L44 |