CSCE 990: AdvancedVLSI Design, Spring 2011

Department of Computer Science and Engineering

University of Nebraska-Lincoln

2:00-3:15 PM, Tu-Th, Avery Hall, Room 118

Quick Links:

Course Announcement

Syllabus

Web Handin

Sources

News & Announcements

Instructor: Sharad C. Seth, Avery Hall, Room 359

Phone: 472-5003
Email: seth at cse dot unl dot edu
Office Hours: TBA (send email to see me, otherwise)

Sources:

Textbooks

J. M. Rabaey, A.Chandrakasan, and B. Nikolic´, Digital Integrated Circuits, Second Edition, Pearson Education, 2003.
N. Weste and D. Harris CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition), Addison Wesley, 2010.

J. Sparsø, Asynchronous circuit design: A Tutorial, draft version available online at: http://webee.technion.ac.il/courses/048878/book.pdf
A. Chandrakasan, W. J. Bowhill, and F. Fox (eds.), Design of High-Performance Microprocessor Circuits, IEEE Press, 2001.

Books and other sources on low-power design

J. Rabaey, Low Power Design Essentials (Integrated Circuits and Systems), Springer, 2009 (Link to Amazon.com) (Link to Springer's online copy available to UNL users)
A. Chandrakasan and R. Broderson (eds.), Low-Power CMOS Design, IEEE Press, 1998.
K. Roy, S. C. Prasad, Low Power CMOS VLSI Circuit Design,Wiley-Interscience, 2000
G. K. Yeap, Practical low power digital VLSI Design, Kluwer, 1998.
V. Zaccaria and V. Zaccaria, Power estimation and optimization methodologies for VLIW-based embedded systems
M. Keating, D. Flynn, R. Aitken, K. Shi, Low power methodology manual: for system-on-chip design
G. Kuo, Closing the power gap between ASIC & custom
Low-Power Design: The engineer's portal to green design

Other sources

Popular

Multi-core processor, Wikipedia article.
T. Sakurai: Alpha Power-Law MOS Model: The author summarizes the inspiration and impact of this classic paper published in JSSC in 1990. You may wish to follow this up by looking at the original paper, available through UNL Libraries online subscription to IEEE journals.
News article about the Angstrom project headed by Prof. Anant Agrawal at MIT that is investigating optical communication and improved electical connections between cores.
A very recent NY Times article, Software Progress Beats Moore's Law by Steve Lohr, March 9, 2011.
Top 11 Technologies of the Decade, IEEE Spectrum, January 2011. The fifth technology listed is Multicore CPUs.

Technical

N. D. E. Jerger, Chip multiprocessor coherence and interconnect system design, PhD dissertation, U. Wisconsin
F. Li, C. Nicopoulos, T. Richardson, Y. Xie,V. Narayanan, M. Kandemir. Design and Management of 3D Chip Multiprocessors Using Network-in-Memory, ISCA'06
Asynchronous systems

S. B. Furber, D. A. Edwards, J. D. Garside. AMULET3: a 100 MIPS asynchronous embedded processor, Proc. ICCD, pp. 329-334, 2000.
H. Gageldonk, K. Berkel, A. Peeters. An asynchronous low power 80C51 microcontroller, Proc. Adv. Res. Asynch. Circuits and Systems, pp. 96-107, 1998.

A survey article, Circuit Design Advances for Wireless Sensing Applications by G. Chen et al., discusses many recent designs for ultralow-power wireless sensors with applications in medical diagnosis, infrastructure monitoring, and environmental sensing, Proc. IEEE, Nov. 2010.

Broad Focus, Surveys

B. Schauer, Multicore Processors – A Necessity, Proquest review
Intel Terascale Research Program
The landscape of parallel computing research: A view from Berkeley
S. Tarzia, A Survey of 3D Circuit Integration, March 2008
Z. Li and C. J. Alpert, What is physical synthesis, ACM/SIGDA E-Newsletter, 41(1), Jan 2011
ITRS 2009
Statistical computing: Definition from the DAC'09 presentation by J. Rabaey (linked below, available from UNL Libraries online subscription) "Computational engines that, given the properties and statistics of the input signals and the physical implementation, ensure that the outputs fall within the desired specifications"

J. Rabaey's DAC'09 presentation
L. Leem, et al. ERSA: Error Resilient System Architecture for Probabilistic Applications, referenced in Rabaey's presentation above.
D. Ernst, et al. RAZOR: Circuit-level detection of timing errors for low-power operation, IEEE MICRO 2005, referenced in Rabaey's presentation above.
Here is a recent paper dealing with system-level design on this topic: Wang, F. Chen, Y. Nicopoulos, C. Wu, X. Xie, Y. Vijaykrishnan, N. “Variation-Aware Task and Communication Mapping for MPSoC Architecture”, IEEE TCAD, February 2011 (available through UNL subscription to IEEE digital library). It may help you identify a good list of prior sources to review.

Hyperphysics is an exploration environment for concepts in physics which employs concept maps and other linking strategies to facilitate smooth navigation.
Richard P. Feynman, Computing Machines in the Future, address at Gakushuin University (Tokyo), on August 9, 1985. Available through Springerlink within UNL at: http://www.springerlink.com/content/ev36x724131u5lm6/

Courses

Link to papers from UCB CS250, Fall 2010: VLSI Systems Design
UCSD ECE260B/CSE241A Low Power VLSI Design, Winter 2010

Business/Companies

Design & Reuse: A website promoting IP-based SoC design.
An example cell library (TSMC 180 nm, 1.8 volt, process from 2001)
MOSIS is a design engineer's single source for a wide variety of semiconductor processes offered by major foundries.

Course Announcement:

Lecture Schedule: (Note: In order to protect the copyright, the overheads from Rabaey's text on low-power design are available on Bb).

Week of	Tuesday		Thursday
Week of	Topics	Assignment	Topics	Assignment
1/10	Class cancelled - snow day		Syllabus, Introduction: Evolution of IC technology	Familiarize yourself with the syllabus and the class web page. Browse through the sources listed in there and start forming ideas for your topic for presentation and project.
1/17	Introduction: Evolution of implementation altenatives and design process	Before the next class, read the Front Matter (7 slides + notes) and Introduction (36 slides + notes) of Rabaey's Low Power Design Essentials (see link to Springer's online copy above). This material is quite accessible so I would like to cover it through discussion in the class.	Discussion of Introduction to low-power design (from Rabaey's textbook)
1/24	Nanometer transistors and their models (Rabaey - Ch. 2)		In-class exercise on nanometer models; Variability and device innovations (Rabaey - Ch. 2)	Complete the in-class exercise. It would be part of the first homework that will be posted before the next class. Read the short article on alpha power-law model by the originator, linked above, then go and read the original paper.
1/31	Power and energy basics (Rabaey - Ch. 3)	Homework 1 on Rabaey, Ch. 2. Due 2/8 at the beginning of the class. You should be getting close to selecting a topic for your presentation and project. Schedule an appointment with me before the end of next week to discuss this.	Power and energy basics (Rabaey - Ch. 3) - continued
2/7	Power and energy basics (Rabaey - Ch. 3) - continued; the method of logical effort for delay and energy optimization (from Weste & Harris, 4e)		Review of the logical effort method (from Harris' presentation)	Homework 2 on Rabaey, Ch. 3 and handouts. Due 2/17 at the beginning of the class.
2/14	Optimizing power at design time (Circuits Level) - I (see Bb for the overheads)		Quick background on tree adders Optimizing power at design time (Circuits Level) - II (see Bb for the overheads)
2/21	Optimizing power at design time (Circuits Level) - II (see Bb for the overheads)+Exracting analysis data from data sheets.			Homework 3 on Rabaey, Ch. 4 and handouts. Due 3/8 at the beginning of the class.
2/28	Presentation schedule, Optimizing power at design time (Arch, Alg., and System) - I.	Note the extension of due date for HW 3.	Optimizing power at design time (Arch, Alg., and System) - I and II.
3/7	Optimizing power at design time (Arch, Alg., and System) - II.		Optimizing power at design time (Arch, Alg., and System) - III.
3/14	Optimizing power at design time - memory (Rabaey, Ch. 7)		Presentation: Bo Liang (zip file of proposal and sources)	Homework 4 on Rabaey, Ch. 5. Due 3/31 at the beginning of the class
3/21	SPRING BREAK	SPRING BREAK	SPRING BREAK	SPRING BREAK
3/28	Presentation: Stephen Mkandawire (zip file of proposal and sources)	Return of Homework 3. Feedback on Homework 3. You will find solutions by Dongyuan posted on Bb.	Presentation: Dongyuan Zhan (zip file of proposal and sources)
4/4	Presentation: Lei Xu (zip file of proposal and sources)		Presentation: Yuji Mo (zip file of proposal and sources)
4/11	Presentation: Pan Yi (zip file of proposal and sources)		Presentation: Ben Christensen (zip file of proposal and sources)
4/18	Low Power SRAM Design		Standby Leakage Power- DRV Control and new L Cache
4/25	Network-on-Chips (NoC): Introduction
5/4	10am-12:30pm, AvH 256C, Final Project Presentations, (Each presentation should be between 20 to 25 minutes)