CSCE430/830: Computer Architecture


Class Time: 1:30P.M. – 2:20P.M., M.W.F.
Class Location: 110 Avery Hall

Office hours: 2:30 P.M. – 3:30 P.M., M.W.F.
Instructor: Dr. Hong Jiang;

Office Location: 214 Schorr Center,

472-6747; jiang@cse.unl.edu

Co-Instructor: Dr. Lei Tian (leitian.hust@gmail.com)

Office Location: 203 Schorr Center

 

 

Syllabus   Course Schedule  Academic Integrity Policy Late Policy  Important Resources  Useful Info  Project Teams   Homework

Required Textbook: John L. Hennessy and David A. Patterson, Computer Architecture -- A Quantitative Approach, 5th Edition, Morgan Kaufmann Publications, Elsevier, Inc., 2012.

 

Useful Info: A very good source of information about the state of computer architecture, plus many reference materials on oral and written communication exist:

 

Late Policy Late work is penalized 20% per day until the following Friday.

 

Academic Integrity Policy: While collaboration on homework is permitted, blatant copying will not be tolerated. Violators, if caught, will subject to penalties ranging from a zero for the homework assignment in question to an F grade for the course, depending on the severity of the violation.

·         The CSE-UNL Academic Integrity Policy

 

Important Resources:

 

Tentative Course Schedule:

Date

Topics

Reading Assignment & References

Assignment Date

Due Date

8/20

Course Syllabus

Fundamentals of Quantitative Design & Analysis

(reference slides from past)

Chapter 1 of text

 

8/22

Fundamentals of Quantitative Design & Analysis

(reference slides from past)

Chapter 1 of text

 

8/24

Fundamentals of Quantitative Design & Analysis

(reference slides from past)

Chapter 1 of text

 

 

8/27

Fundamentals of Quantitative Design & Analysis

(reference slides from past)

Chapter 1 of text

8/29

Fundamentals of Quantitative Design & Analysis

(reference slides from past)

Chapter 1 of text

HW-1

 

8/31

Review of Chapter 1 and exercises

Chapter 1 of text

 

 

9/5

Memory Hierarchy Design

(reference slides from past)

Chapter 2 and Appendix B of the Textbook

 

HW-1

9/7

Memory Hierarchy Design

(reference slides from past)

Chapter 2 and Appendix B of the Textbook

 

 

9/10

Memory Hierarchy Design

(reference slides from past)

Chapter 2 and Appendix B of the Textbook

 

 

9/12

Memory Hierarchy Design

(reference slides from past)

Chapter 2 and Appendix B of the Textbook

 

 

9/14

Memory Hierarchy Design

(reference slides from past)

Chapter 2 and Appendix B of the Textbook

 

 

9/17

Memory Hierarchy Design

(reference slides from past)

Chapter 2 and Appendix B of the Textbook

HW-2

 

9/19

Memory Hierarchy Design

(reference slides from past)

Chapter 2 and Appendix B of the Textbook

 

 

9/21

Memory Hierarchy Design

(reference slides from past)

Chapter 2 and Appendix B of the Textbook

Project Specs

Helpful Literature

 

9/24

Memory Hierarchy Design

(reference slides from past)

Chapter 2 and Appendix B of the Textbook

 

 

9/26

Memory Hierarchy Design

(reference slides from past)

Chapter 2 and Appendix B of the Textbook

 

HW-2

9/28

Memory Hierarchy Design

(reference slides from past)

Chapter 2 and Appendix B of the Textbook

Project Specs

 

 

10/1

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

 

 

10/3

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

 

 

10/5

Introduction to Storage Systems (1): Disks and RAID

Appendix D (online)

 

 

10/8

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

 

 

10/10

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

 

 

10/12

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

HW-3

 

10/17

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

 

 

10/19

Review of Chapters 1, 2, and Appendix C

Chapter 3 and Appendix C of the Textbook

 

 

10/22

In-Class Exam I, covering Chapters 1, 2, and Appendix C

Open book and notes

 

 

10/24

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

 

HW-3

10/26

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

 

 

10/29

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

 

 

10/31

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

 

 

11/2

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

 

 

11/5

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

 

 

11/7

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

 

 

11/9

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

 

 

11/12

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

 

 

11/14

Presentation by GARMIN representatives, Ted Mabie and Jessica Zlab, about GARMIN & its embedded systems software development

HW-4

 

11/16

Instruction-Level Parallelism and Its Exploitation

(reference slides from past)

Chapter 3 and Appendix C of the Textbook

 

 

11/19

Data-Level Parallelism and Its Exploitation in Vector, SIMD, and GPU Architectures

Chapter 4 of the Textbook

 

 

11/26

Data-Level Parallelism and Its Exploitation in Vector, SIMD, and GPU Architectures

Chapter 4 of the Textbook

 

HW-4

11/28

Data-Level Parallelism and Its Exploitation in Vector, SIMD, and GPU Architectures

Chapter 4 of the Textbook

HW-5

 

12/3

Review of Chapters 3 & 4

Chapters 3 & 4 of the Textbook

 

 

12/5

Q & A Session

 

HW-5

12/7

Project Presentations (1:30pm—3:30pm)

 

 

 

12/12

In-Class Exam II, covering Chapters 3 & 4 (1:00pm—2:00pm)

 

 

 

 

 

 

 

 

 

 

Project Teams:

Team Name

Names of Team Members

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 


Summary of Homework:

1. Assignment #1: Due Midnight, Wednesday, September 5, 2012

2. Assignment #2: Due Midnight, Wednesday, September 26, 2012

3. Assignment #3: Due Midnight, Wednesday, October 24, 2012

4. Assignment #4: Due Midnight, Monday, November 26, 2012

5. Assignment #5: Due Midnight, Wednesday, December 5, 2012