| Week of...
| Week #
|
| Monday
| Tuesday
| Wednesday
| Thursday
| Friday
|
| 12 Jan
| Week 1
| Date
Lecture
Topic
Lab
Homework
| 12 Jan
Chapter 1: Binary Numbers
Number Systems and Conversions
| 13 Jan
Lab 1 Start
| 14 Jan
Chapter 1: Binary Numbers
Addition/Subtraction of
Signed/Unsigned Numbers
Lab 1 Start
| 15 Jan
| 16 Jan
Chapter 1: Binary Numbers
Multiplication/Division and
Zero/Sign Extension
|
| 19 Jan
| Week 2
| Date
Lecture
Topic
Lab
Homework
| 19 Jan
MLK Day! - No Class
| 20 Jan
Lab 2 Start
Lab 1: Due at Midnight
| 21 Jan
Ch 2 & App B: Basic Assembly Lang
Assembly Language Basics
Lab 2 Start
| 22 Jan
| 23 Jan
Ch 2 & App B: Basic Assembly Lang
Arithmetic and Branching Instructions
|
| 26 Jan
| Week 3
| Date
Lecture
Topic
Lab
Homework
| 26 Jan
Ch 2 & App B: Basic Assembly Lang
Logic, Move, Shift, and Rotate Instr
Lab 2: Due at Midnight
Homework 1: Due Midnight Sunday
| 27 Jan
Lab 3 Start
| 28 Jan
Ch 2 & App B: Basic Assembly Lang
Load/Store Instr and Directives
Lab 3 Start
| 29 Jan
| 30 Jan
Ch 2 & App B: Basic Assembly Lang
Subroutine Instr and Stack
|
| 2 Feb
| Week 4
| Date
Lecture
Topic
Lab
Homework
| 2 Feb
Ch 2 & App B: Basic Assembly Lang
Nested Subroutines
Lab 3: Due at Midnight
| 3 Feb
Lab 4 Start
| 4 Feb
Ch 3 & App B: I/O Assembly
Polling
Lab 4 Start
| 5 Feb
| 6 Feb
Ch 3 & App B: I/O Assembly
Interrupts
|
| 9 Feb
| Week 5
| Date
Lecture
Topic
Lab
Homework
| 9 Feb
App A: Logic circuit and VHDL
Logic Gates, Logic Rules, & Synthesis
Lab 4: Due at Midnight
Homework 2: Due Midnight Sunday
| 10 Feb
Lab 5 Start
| 11 Feb
App A: Logic circuit and VHDL
K-Maps and VHDL Intro
Lab 5 Start
| 12 Feb
Exam 1 at DLC
| 13 Feb
Exam 1 at DLC
|
| 16 Feb
| Week 6
| Date
Lecture
Topic
Lab
Homework
| 16 Feb
App A: Logic circuit and VHDL
VHDL Intro, Data Types, and CSAs
Lab 5: Due at Midnight
Advising/Counselings Start
| 17 Feb
Lab 6 Start
| 18 Feb
App A: Logic circuit and VHDL
VHDL Intro Part 2
Lab 6 Start
| 19 Feb
| 20 Feb
App A: Logic circuit and VHDL
Sequential Circuits
|
| 23 Feb
| Week 7
| Date
Lecture
Topic
Lab
Homework
| 23 Feb
App A: Logic circuit and VHDL
Flip-Flops, Registers, & Seq Circuits
Lab 6: Due at Midnight
Advising/Counseling Week 2
| 24 Feb
Lab 7 Start
| 25 Feb
App A: Logic circuit and VHDL
FSM Design
Lab 7 Start
| 26 Feb
| 27 Feb
App A: Logic circuit and VHDL
FSM Analysis
|
| 2 Mar
| Week 8
| Date
Lecture
Topic
Lab
Homework
| 2 Mar
App A: Logic circuit and VHDL
VHDL Concurrent vs Sequential
Advising/Counseling Week 3
| 3 Mar
| 4 Mar
App A: Logic circuit and VHDL
VHDL Synthesis and VHDL FSMs
| 5 Mar
| 6 Mar
Ch 5: Processor Design & Nios Proc
Nios CPU Overview & Reg File
|
| 9 Mar
| Week 9
| Date
Lecture
Topic
Lab
Homework
| 9 Mar
Ch 5: Processor Design & Nios Proc
Arithmetic Logic Unit
Lab 7: Due at Midnight
Homework 3: Due Midnight Sunday
| 10 Mar
Lab 8 Start
| 11 Mar
Ch 5: Processor Design & Nios Proc
Nios Instruction Set & Arithmetic
Instructions
Lab 8 Start
Last week of Advising/Counseling
| 12 Mar
Exam 2 at DLC
| 13 Mar
No Class/Lecture
Exam 2 at DLC
Advising/Counseling Sessions Due!
|
| 16 Mar
| Week 10
| Date
Lecture
Topic
Lab
Homework
| 16 Mar
Spring Break! - No Class
| 17 Mar
Spring Break! - No Class
| 18 Mar
Spring Break! - No Class
| 19 Mar
Spring Break! - No Class
| 20 Mar
Spring Break! - No Class
|
| 23 Mar
| Week 11
| Date
Lecture
Topic
Lab
Homework
| 23 Mar
Ch 5: Processor Design & Nios Proc
Logic, Data Copy, & Control Transfer
Instructions
Lab 8: Due at Midnight
| 24 Mar
Lab 9 Start
| 25 Mar
Ch 5: Processor Design & Nios Proc
Lab 9 Start
| 26 Mar
| 27 Mar
Chapter 5: Datapath
|
| 30 Mar
| Week 12
| Date
Lecture
Topic
Lab
Homework
| 30 Mar
Chapter 5: Datapath
Group Lab 1: Due Midnight Sunday
| 31 Mar
| 1 Apr
Chapter 5: Control Signals
| 2 Apr
| 3 Apr
Chapter 4: Assembler
Assembler and Processor Example
|
| 6 Apr
| Week 13
| Date
Lecture
Topic
Lab
Homework
| 6 Apr
Chapter 8: Memory
Sequential Building Blocks &
Memory Types
Lab 9: Due at Midnight
Homework 4: Due Midnight Sunday
| 7 Apr
| 8 Apr
Chapter 8: Memory
Memory Hierarchy & Cache Memory
| 9 Apr
| 10 Apr
Chapter 8: Memory
Cache Write Requests, Cache Design,
& Replacement Algorithms
|
| 13 Apr
| Week 14
| Date
Lecture
Topic
Lab
Homework
| 13 Apr
Chapter 8: Memory
Virtual Memory
Group Lab 2: Due Midnight Sunday
| 14 Apr
| 15 Apr
Ch 11 & App A: Logic Arrays
| 16 Apr
| 17 Apr
Chapter 6: Pipelining
|
| 20 Apr
| Week 15
| Date
Lecture
Topic
Lab
Homework
| 20 Apr
Exam Review
Homework 5: Due Midnight Monday
| 21 Apr
Group Lab 3: Due at Midnight
| 22 Apr
Exam Review
| 23 Apr
Exam 3 at DLC
| 24 Apr
No Class/Lecture
Exam 3 at DLC
|
| 27 Apr
| Week 16
| Date
Lecture
Topic
Lab
Homework
| 27 Apr
No Class/Lecture
Group Lab 4: Due Midnight Sunday
| 28 Apr
| 29 Apr
Final Exam Review and Board Turn-in
| 30 Apr
| 1 May
Group Lab 5 Final Report: Due at Midnight
|
| 4 May
| Week 17
| Date
Topic
| 4 May
Finals Exam at DLC
| 5 May
Finals Exam at DLC
| 6 May
Finals Exam at DLC
| 7 May
Finals Week
| 8 May
Finals Week
|