CSCE/RAIK 284H Foundations of Computer Systems

Spring 2010
TTh 9:00-10:45am, Kauffman 112

Instructor: Dr. Steve Goddard

Avery 256, 472-2401
Office hours: Avery 256, 11:00am-12:30pm TuTh

Semester Project

This semester you will build a 8-bit RISC processor using the Altera Quartus II software and an Altera UP2 FPGA. This will be a single-cycle processor consisting of a ROM component for storing instructions, a decoder for interpreting instructions, an ALU for performing operations, and a RAM unit for loading and storing register values. You also will be writing an assembler to build programs for your processor and writing a an assembly program to run on your processor. You will then download your finished program and processor to the Altera board to demonstrate its completeness. To accomplish all of this, you will be working in teams of two.

Project Description

There are a four deliverable dates:

April 11, 2010: Assembler and first draft of assembly program
April 18, 2010: Program registers, ALU, and test cases
April 25, 2010: Fetch, decode, memory-mapped I/O, and test cases
April 28, 2010: Complete processor, assembler, and assembly program
You will also demonstrate your processor for the instructor and TA. These presentations will be during dead week; a sign-up for times will be posted closer to the due date.

Related project files in zip format
display.mif file