Altera SOPC Builder Version 6.00 Build 178
Copyright (c) 1999-2006 Altera Corporation.  All rights reserved.


# 2007.04.08 00:24:07 (*) mk_custom_sdk starting
# 2007.04.08 00:24:07 (*) Reading project C:/csce496/final_project/PROCESSOR/system_0.ptf.

# 2007.04.08 00:24:08 (*) Finding all CPUs
# 2007.04.08 00:24:08 (*) Finding all available components
# 2007.04.08 00:24:08 (*) Reading C:/csce496/final_project/PROCESSOR/.sopc_builder/install.ptf

# 2007.04.08 00:24:08 (*) Found 60 components

# 2007.04.08 00:24:08 (*) Finding all peripherals

# 2007.04.08 00:24:08 (*) Finding software components

# 2007.04.08 00:24:09 (*) (Legacy SDK Generation Skipped)
# 2007.04.08 00:24:09 (*) (All TCL Script Generation Skipped)
# 2007.04.08 00:24:09 (*) (No Libraries Built)
# 2007.04.08 00:24:09 (*) (Contents Generation Skipped)
# 2007.04.08 00:24:09 (*) mk_custom_sdk finishing
# 2007.04.08 00:24:09 (*) Starting generation for system: system_0.

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# 2007.04.08 00:24:10 (*) Running Generator Program for cpu_0

# 2007.04.08 00:24:14 (*)   Checking for plaintext license.
# 2007.04.08 00:24:14 (*)   Plaintext license not found.
# 2007.04.08 00:24:14 (*)   Checking for encrypted license (non-evaluation).
# 2007.04.08 00:24:14 (*)   Encrypted license not found.  Defaulting to OCP evaluation license (produces a time-limited SOF)
# 2007.04.08 00:24:23 (*)   Creating encrypted HDL

# 2007.04.08 00:24:25 (*) Running Generator Program for cfi_flash_0

# 2007.04.08 00:24:26 (*) Running Generator Program for sdram_0

# 2007.04.08 00:24:27 (*) Running Generator Program for jtag_uart_0

# 2007.04.08 00:24:28 (*) Running Generator Program for timer_0

# 2007.04.08 00:24:29 (*) Running Generator Program for timer_1

# 2007.04.08 00:24:30 (*) Running Generator Program for button_pio

# 2007.04.08 00:24:31 (*) Running Generator Program for sram_0

# 2007.04.08 00:24:33 (*) Running Generator Program for clock_0

# 2007.04.08 00:24:34 (*) Running Generator Program for clock_1

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# 2007.04.08 00:24:35 (*) Running Test Generator Program for sdram_0

# 2007.04.08 00:24:36 (*) Making arbitration and system (top) modules.

# 2007.04.08 00:24:56 (*) Generating Quartus symbol for top level: system_0

# 2007.04.08 00:24:56 (*) Symbol C:/csce496/final_project/PROCESSOR/system_0.bsf already exists, no need to regenerate
# 2007.04.08 00:24:56 (*) Creating command-line system-generation script: C:/csce496/final_project/PROCESSOR/system_0_generation_script

# 2007.04.08 00:24:56 (*) Running setup for HDL simulator: modelsim


# 2007.04.08 00:24:56 (*) Setting up Quartus with system_0_setup_quartus.tcl
c:/altera/quartus60/bin/quartus_sh -t system_0_setup_quartus.tcl


Info: *******************************************************************
Info: Running Quartus II Shell
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Copyright (C) 1991-2006 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Altera Program License 
    Info: Subscription Agreement, Altera MegaCore Function License 
    Info: Agreement, or other applicable license agreement, including, 
    Info: without limitation, that your use is for the sole purpose of 
    Info: programming logic devices manufactured by Altera and sold by 
    Info: Altera or its authorized distributors.  Please refer to the
 
    Info: applicable agreement for further details.
    Info: Processing started: Sun Apr 08 00:24:57 2007
Info: Command: quartus_sh -t system_0_setup_quartus.tcl
Info: Evaluation of Tcl script system_0_setup_quartus.tcl was successful
Info: Quartus II Shell was successful. 0 errors, 0 warnings
    Info: Processing ended: Sun Apr 08 00:24:57 2007
    Info: Elapsed time: 00:00:00

# 2007.04.08 00:24:57 (*) Completed generation for system: system_0.
# 2007.04.08 00:24:57 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED:
  SOPC Builder database : C:/csce496/final_project/PROCESSOR/system_0.ptf 
  System HDL Model : C:/csce496/final_project/PROCESSOR/system_0.v 
  System Generation Script : C:/csce496/final_project/PROCESSOR/system_0_generation_script 

# 2007.04.08 00:24:57 (*) SUCCESS: SYSTEM GENERATION COMPLETED.


Press 'Exit' to exit.
