Analysis & Synthesis report for DE2_NIOS_DEVICE_LED
Sun Apr 08 00:52:28 2007
Version 6.0 Build 178 04/27/2006 SJ Web Edition


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Analysis & Synthesis DSP Block Usage Summary
  9. State Machine - |DE2_NIOS_DEVICE_LED|I2C_AV_Config:u1|mSetup_ST
 10. State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_state
 11. State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_next
 12. State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_state
 13. State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_next
 14. State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state
 15. State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state
 16. State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state
 17. State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state
 18. State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize
 19. Registers Protected by Synthesis
 20. Logic Cells Representing Combinational Loops
 21. General Register Statistics
 22. Inverted Register Statistics
 23. Multiplexer Restructuring Statistics (Restructuring Performed)
 24. Source assignments for system_0:u0|clock_0:the_clock_0
 25. Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync
 26. Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync
 27. Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync
 28. Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync
 29. Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_bit_pipe:endofpacket_bit_pipe
 30. Source assignments for system_0:u0|clock_1:the_clock_1
 31. Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync
 32. Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync
 33. Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync
 34. Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync
 35. Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_bit_pipe:endofpacket_bit_pipe
 36. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated
 37. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1
 38. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_tke1:auto_generated
 39. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated
 40. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated|altsyncram_pfn1:altsyncram1
 41. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_4be1:auto_generated
 42. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_5be1:auto_generated
 43. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_vf22:auto_generated
 44. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated
 45. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result
 46. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result
 47. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated
 48. Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated
 49. Source assignments for system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2
 50. Source assignments for system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2
 51. Source assignments for system_0:u0|sdram_0:the_sdram_0
 52. Source assignments for system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave
 53. Source assignments for system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch
 54. Source assignments for system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch
 55. Source assignments for sld_hub:sld_hub_inst
 56. Source assignments for sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine
 57. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 58. Source assignments for I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_mj01:auto_generated
 59. Parameter Settings for User Entity Instance: SDRAM_PLL:PLL1|altpll:altpll_component
 60. Parameter Settings for User Entity Instance: Audio_PLL:PLL2|altpll:altpll_component
 61. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data
 62. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram
 63. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag
 64. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram
 65. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht
 66. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram
 67. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a
 68. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram
 69. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b
 70. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram
 71. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag
 72. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram
 73. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data
 74. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram
 75. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1
 76. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2
 77. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component
 78. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 79. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component
 80. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
 81. Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1
 82. Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo
 83. Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo
 84. Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic
 85. Parameter Settings for User Entity Instance: I2C_AV_Config:u1
 86. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 87. Parameter Settings for Inferred Entity Instance: I2C_AV_Config:u1|altsyncram:Ram0_rtl_0
 88. altmult_add Parameter Settings by Entity Instance
 89. scfifo Parameter Settings by Entity Instance
 90. Analysis & Synthesis Messages
 91. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
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(including device programming or simulation files), and any 
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without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
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+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                 ;
+------------------------------------+-----------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sun Apr 08 00:52:28 2007   ;
; Quartus II Version                 ; 6.0 Build 178 04/27/2006 SJ Web Edition ;
; Revision Name                      ; DE2_NIOS_DEVICE_LED                     ;
; Top-level Entity Name              ; DE2_NIOS_DEVICE_LED                     ;
; Family                             ; Cyclone II                              ;
; Total logic elements               ; 3554                                    ;
; Total registers                    ; 2770                                    ;
; Total pins                         ; 429                                     ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 72,192                                  ;
; Embedded Multiplier 9-bit elements ; 4                                       ;
; Total PLLs                         ; 1                                       ;
+------------------------------------+-----------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                  ;
+--------------------------------------------------------------------+---------------------+---------------------+
; Option                                                             ; Setting             ; Default Value       ;
+--------------------------------------------------------------------+---------------------+---------------------+
; Device                                                             ; EP2C35F672C6        ;                     ;
; Top-level entity name                                              ; DE2_NIOS_DEVICE_LED ; DE2_NIOS_DEVICE_LED ;
; Family name                                                        ; Cyclone II          ; Stratix             ;
; Use smart compilation                                              ; Off                 ; Off                 ;
; Restructure Multiplexers                                           ; Auto                ; Auto                ;
; Create Debugging Nodes for IP Cores                                ; Off                 ; Off                 ;
; Preserve fewer node names                                          ; On                  ; On                  ;
; Disable OpenCore Plus hardware evaluation                          ; Off                 ; Off                 ;
; Verilog Version                                                    ; Verilog_2001        ; Verilog_2001        ;
; VHDL Version                                                       ; VHDL93              ; VHDL93              ;
; State Machine Processing                                           ; Auto                ; Auto                ;
; Extract Verilog State Machines                                     ; On                  ; On                  ;
; Extract VHDL State Machines                                        ; On                  ; On                  ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                  ; On                  ;
; DSP Block Balancing                                                ; Auto                ; Auto                ;
; Maximum DSP Block Usage                                            ; Unlimited           ; Unlimited           ;
; NOT Gate Push-Back                                                 ; On                  ; On                  ;
; Power-Up Don't Care                                                ; On                  ; On                  ;
; Remove Redundant Logic Cells                                       ; Off                 ; Off                 ;
; Remove Duplicate Registers                                         ; On                  ; On                  ;
; Ignore CARRY Buffers                                               ; Off                 ; Off                 ;
; Ignore CASCADE Buffers                                             ; Off                 ; Off                 ;
; Ignore GLOBAL Buffers                                              ; Off                 ; Off                 ;
; Ignore ROW GLOBAL Buffers                                          ; Off                 ; Off                 ;
; Ignore LCELL Buffers                                               ; Off                 ; Off                 ;
; Ignore SOFT Buffers                                                ; On                  ; On                  ;
; Limit AHDL Integers to 32 Bits                                     ; Off                 ; Off                 ;
; Optimization Technique -- Cyclone II                               ; Balanced            ; Balanced            ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                  ; 70                  ;
; Auto Carry Chains                                                  ; On                  ; On                  ;
; Auto Open-Drain Pins                                               ; On                  ; On                  ;
; Remove Duplicate Logic                                             ; On                  ; On                  ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                 ; Off                 ;
; Perform gate-level register retiming                               ; Off                 ; Off                 ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                  ; On                  ;
; Auto ROM Replacement                                               ; On                  ; On                  ;
; Auto RAM Replacement                                               ; On                  ; On                  ;
; Auto Shift Register Replacement                                    ; On                  ; On                  ;
; Auto Clock Enable Replacement                                      ; On                  ; On                  ;
; Allow Synchronous Control Signals                                  ; On                  ; On                  ;
; Force Use of Synchronous Clear Signals                             ; Off                 ; Off                 ;
; Auto Resource Sharing                                              ; Off                 ; Off                 ;
; Allow Any RAM Size For Recognition                                 ; Off                 ; Off                 ;
; Allow Any ROM Size For Recognition                                 ; Off                 ; Off                 ;
; Allow Any Shift Register Size For Recognition                      ; Off                 ; Off                 ;
; Maximum Number of M4K Memory Blocks                                ; Unlimited           ; Unlimited           ;
; Ignore translate_off and translate_on Synthesis Directives         ; Off                 ; Off                 ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                  ; On                  ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                 ; Off                 ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                   ; 2                   ;
; PowerPlay Power Optimization                                       ; Normal compilation  ; Normal compilation  ;
; HDL message level                                                  ; Level2              ; Level2              ;
+--------------------------------------------------------------------+---------------------+---------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                        ;
+-----------------------------------+-----------------+----------------------------------+----------------------------------------------------------------------+
; File Name with User-Entered Path  ; Used in Netlist ; File Type                        ; File Name with Absolute Path                                         ;
+-----------------------------------+-----------------+----------------------------------+----------------------------------------------------------------------+
; Audio_PLL.v                       ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/Audio_PLL.v                       ;
; button_pio.v                      ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/button_pio.v                      ;
; cpu_0.v                           ; yes             ; Encrypted User Verilog HDL File  ; C:/csce496/final_project/PROCESSOR/cpu_0.v                           ;
; cpu_0_jtag_debug_module.v         ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/cpu_0_jtag_debug_module.v         ;
; cpu_0_jtag_debug_module_wrapper.v ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/cpu_0_jtag_debug_module_wrapper.v ;
; cpu_0_mult_cell.v                 ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/cpu_0_mult_cell.v                 ;
; cpu_0_test_bench.v                ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/cpu_0_test_bench.v                ;
; DE2_NIOS_DEVICE_LED.v             ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v             ;
; I2C_AV_Config.v                   ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/I2C_AV_Config.v                   ;
; I2C_Controller.v                  ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/I2C_Controller.v                  ;
; jtag_uart_0.v                     ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/jtag_uart_0.v                     ;
; Reset_Delay.v                     ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/Reset_Delay.v                     ;
; sdram_0.v                         ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/sdram_0.v                         ;
; SDRAM_PLL.v                       ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/SDRAM_PLL.v                       ;
; sram_0.v                          ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/sram_0.v                          ;
; SRAM_16Bit_512K.v                 ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/SRAM_16Bit_512K.v                 ;
; system_0.v                        ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/system_0.v                        ;
; timer_0.v                         ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/timer_0.v                         ;
; timer_1.v                         ; yes             ; User Verilog HDL File            ; C:/csce496/final_project/PROCESSOR/timer_1.v                         ;
; altpll.tdf                        ; yes             ; Megafunction                     ; c:/altera/quartus60/libraries/megafunctions/altpll.tdf               ;
; aglobal60.inc                     ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/aglobal60.inc            ;
; stratix_pll.inc                   ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/stratix_pll.inc          ;
; stratixii_pll.inc                 ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/stratixii_pll.inc        ;
; cycloneii_pll.inc                 ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/cycloneii_pll.inc        ;
; clock_0.v                         ; yes             ; Other                            ; C:/csce496/final_project/PROCESSOR/clock_0.v                         ;
; clock_1.v                         ; yes             ; Other                            ; C:/csce496/final_project/PROCESSOR/clock_1.v                         ;
; altsyncram.tdf                    ; yes             ; Megafunction                     ; c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf           ;
; stratix_ram_block.inc             ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/stratix_ram_block.inc    ;
; lpm_mux.inc                       ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/lpm_mux.inc              ;
; lpm_decode.inc                    ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/lpm_decode.inc           ;
; altsyncram.inc                    ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/altsyncram.inc           ;
; a_rdenreg.inc                     ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/a_rdenreg.inc            ;
; altrom.inc                        ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/altrom.inc               ;
; altram.inc                        ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/altram.inc               ;
; altdpram.inc                      ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/altdpram.inc             ;
; altqpram.inc                      ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/altqpram.inc             ;
; db/altsyncram_cub1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/altsyncram_cub1.tdf            ;
; db/altsyncram_k1l1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/altsyncram_k1l1.tdf            ;
; db/altsyncram_tke1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/altsyncram_tke1.tdf            ;
; db/altsyncram_q8e1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/altsyncram_q8e1.tdf            ;
; db/altsyncram_pfn1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/altsyncram_pfn1.tdf            ;
; db/altsyncram_4be1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/altsyncram_4be1.tdf            ;
; db/altsyncram_5be1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/altsyncram_5be1.tdf            ;
; db/altsyncram_vf22.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/altsyncram_vf22.tdf            ;
; db/altsyncram_a422.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/altsyncram_a422.tdf            ;
; altmult_add.tdf                   ; yes             ; Megafunction                     ; c:/altera/quartus60/libraries/megafunctions/altmult_add.tdf          ;
; stratix_mac_mult.inc              ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/stratix_mac_mult.inc     ;
; stratix_mac_out.inc               ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/stratix_mac_out.inc      ;
; db/mult_add_4cr2.tdf              ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/mult_add_4cr2.tdf              ;
; db/ded_mult_2o81.tdf              ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/ded_mult_2o81.tdf              ;
; db/dffpipe_93c.tdf                ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/dffpipe_93c.tdf                ;
; db/mult_add_6cr2.tdf              ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/mult_add_6cr2.tdf              ;
; db/altsyncram_c572.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/altsyncram_c572.tdf            ;
; db/altsyncram_e502.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/altsyncram_e502.tdf            ;
; scfifo.tdf                        ; yes             ; Megafunction                     ; c:/altera/quartus60/libraries/megafunctions/scfifo.tdf               ;
; a_regfifo.inc                     ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/a_regfifo.inc            ;
; a_dpfifo.inc                      ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/a_dpfifo.inc             ;
; a_i2fifo.inc                      ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/a_i2fifo.inc             ;
; a_fffifo.inc                      ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/a_fffifo.inc             ;
; a_f2fifo.inc                      ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/a_f2fifo.inc             ;
; db/scfifo_1n21.tdf                ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/scfifo_1n21.tdf                ;
; db/a_dpfifo_8t21.tdf              ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/a_dpfifo_8t21.tdf              ;
; db/a_fefifo_7cf.tdf               ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/a_fefifo_7cf.tdf               ;
; db/cntr_rj7.tdf                   ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/cntr_rj7.tdf                   ;
; db/dpram_5h21.tdf                 ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/dpram_5h21.tdf                 ;
; db/altsyncram_9tl1.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/altsyncram_9tl1.tdf            ;
; db/cntr_dl8.tdf                   ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/cntr_dl8.tdf                   ;
; alt_jtag_atlantic.v               ; yes             ; Encrypted Megafunction           ; c:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v      ;
; sld_hub.vhd                       ; yes             ; Encrypted Megafunction           ; c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd              ;
; lpm_shiftreg.tdf                  ; yes             ; Megafunction                     ; c:/altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf         ;
; lpm_constant.inc                  ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/lpm_constant.inc         ;
; dffeea.inc                        ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/dffeea.inc               ;
; lpm_decode.tdf                    ; yes             ; Megafunction                     ; c:/altera/quartus60/libraries/megafunctions/lpm_decode.tdf           ;
; declut.inc                        ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/declut.inc               ;
; altshift.inc                      ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/altshift.inc             ;
; lpm_compare.inc                   ; yes             ; Other                            ; c:/altera/quartus60/libraries/megafunctions/lpm_compare.inc          ;
; db/decode_aoi.tdf                 ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/decode_aoi.tdf                 ;
; sld_dffex.vhd                     ; yes             ; Encrypted Megafunction           ; c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd            ;
; sld_rom_sr.vhd                    ; yes             ; Encrypted Megafunction           ; c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd           ;
; db/altsyncram_mj01.tdf            ; yes             ; Auto-Generated Megafunction      ; C:/csce496/final_project/PROCESSOR/db/altsyncram_mj01.tdf            ;
+-----------------------------------+-----------------+----------------------------------+----------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                ;
+---------------------------------------------+----------------------------------------------+
; Resource                                    ; Usage                                        ;
+---------------------------------------------+----------------------------------------------+
; Estimated Total logic elements              ; 3,554                                        ;
; Total combinational functions               ; 3554                                         ;
; Logic element usage by number of LUT inputs ;                                              ;
;     -- 4 input functions                    ; 1883                                         ;
;     -- 3 input functions                    ; 1072                                         ;
;     -- <=2 input functions                  ; 599                                          ;
;         -- Combinational cells for routing  ; 0                                            ;
; Logic elements by mode                      ;                                              ;
;     -- normal mode                          ; 3213                                         ;
;     -- arithmetic mode                      ; 341                                          ;
; Total registers                             ; 2770                                         ;
; I/O pins                                    ; 429                                          ;
; Total memory bits                           ; 72192                                        ;
; Embedded Multiplier 9-bit elements          ; 4                                            ;
; Total PLLs                                  ; 1                                            ;
; Maximum fan-out node                        ; SDRAM_PLL:PLL1|altpll:altpll_component|_clk0 ;
; Maximum fan-out                             ; 2302                                         ;
; Total fan-out                               ; 26853                                        ;
; Average fan-out                             ; 3.84                                         ;
+---------------------------------------------+----------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+-------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                                                                      ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                                                                                                    ;
+-------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |DE2_NIOS_DEVICE_LED                                                                            ; 3554 (1)          ; 2770 (0)     ; 72192       ; 0    ; 4            ; 0       ; 2         ; 429  ; 0            ; |DE2_NIOS_DEVICE_LED                                                                                                                                                                                                                                                   ;
;    |I2C_AV_Config:u1|                                                                           ; 87 (39)           ; 57 (28)      ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|I2C_AV_Config:u1                                                                                                                                                                                                                                  ;
;       |I2C_Controller:u0|                                                                       ; 48 (48)           ; 29 (29)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|I2C_AV_Config:u1|I2C_Controller:u0                                                                                                                                                                                                                ;
;       |altsyncram:Ram0_rtl_0|                                                                   ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|I2C_AV_Config:u1|altsyncram:Ram0_rtl_0                                                                                                                                                                                                            ;
;          |altsyncram_mj01:auto_generated|                                                       ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_mj01:auto_generated                                                                                                                                                                             ;
;    |Reset_Delay:delay1|                                                                         ; 33 (33)           ; 25 (25)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|Reset_Delay:delay1                                                                                                                                                                                                                                ;
;    |SDRAM_PLL:PLL1|                                                                             ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|SDRAM_PLL:PLL1                                                                                                                                                                                                                                    ;
;       |altpll:altpll_component|                                                                 ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|SDRAM_PLL:PLL1|altpll:altpll_component                                                                                                                                                                                                            ;
;    |sld_hub:sld_hub_inst|                                                                       ; 92 (37)           ; 68 (7)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst                                                                                                                                                                                                                              ;
;       |lpm_decode:instruction_decoder|                                                          ; 5 (0)             ; 5 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder                                                                                                                                                                                               ;
;          |decode_aoi:auto_generated|                                                            ; 5 (5)             ; 5 (5)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated                                                                                                                                                                     ;
;       |lpm_shiftreg:jtag_ir_register|                                                           ; 0 (0)             ; 10 (10)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register                                                                                                                                                                                                ;
;       |sld_dffex:BROADCAST|                                                                     ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|sld_dffex:BROADCAST                                                                                                                                                                                                          ;
;       |sld_dffex:IRF_ENA_0|                                                                     ; 0 (0)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0                                                                                                                                                                                                          ;
;       |sld_dffex:IRF_ENA|                                                                       ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA                                                                                                                                                                                                            ;
;       |sld_dffex:IRSR|                                                                          ; 4 (4)             ; 7 (7)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|sld_dffex:IRSR                                                                                                                                                                                                               ;
;       |sld_dffex:RESET|                                                                         ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|sld_dffex:RESET                                                                                                                                                                                                              ;
;       |sld_dffex:\GEN_IRF:1:IRF|                                                                ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF                                                                                                                                                                                                     ;
;       |sld_dffex:\GEN_IRF:2:IRF|                                                                ; 2 (2)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF                                                                                                                                                                                                     ;
;       |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|                                                       ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF                                                                                                                                                                                            ;
;       |sld_dffex:\GEN_SHADOW_IRF:2:S_IRF|                                                       ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:2:S_IRF                                                                                                                                                                                            ;
;       |sld_jtag_state_machine:jtag_state_machine|                                               ; 19 (19)           ; 19 (19)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine                                                                                                                                                                                    ;
;       |sld_rom_sr:HUB_INFO_REG|                                                                 ; 22 (22)           ; 9 (9)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG                                                                                                                                                                                                      ;
;    |system_0:u0|                                                                                ; 3341 (1)          ; 2620 (0)     ; 71168       ; 0    ; 4            ; 0       ; 2         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0                                                                                                                                                                                                                                       ;
;       |button_pio:the_button_pio|                                                               ; 14 (14)           ; 20 (20)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|button_pio:the_button_pio                                                                                                                                                                                                             ;
;       |button_pio_s1_arbitrator:the_button_pio_s1|                                              ; 2 (2)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|button_pio_s1_arbitrator:the_button_pio_s1                                                                                                                                                                                            ;
;       |clock_0:the_clock_0|                                                                     ; 33 (17)           ; 130 (112)    ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0                                                                                                                                                                                                                   ;
;          |clock_0_edge_to_pulse:read_done_edge_to_pulse|                                        ; 0 (0)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse                                                                                                                                                                     ;
;          |clock_0_edge_to_pulse:read_request_edge_to_pulse|                                     ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_edge_to_pulse:read_request_edge_to_pulse                                                                                                                                                                  ;
;          |clock_0_edge_to_pulse:write_request_edge_to_pulse|                                    ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_edge_to_pulse:write_request_edge_to_pulse                                                                                                                                                                 ;
;          |clock_0_master_FSM:master_FSM|                                                        ; 8 (8)             ; 6 (6)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM                                                                                                                                                                                     ;
;          |clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|                   ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync                                                                                                                                                ;
;          |clock_0_slave_FSM:slave_FSM|                                                          ; 5 (5)             ; 3 (3)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM                                                                                                                                                                                       ;
;          |clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|               ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync                                                                                                                                            ;
;          |clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|             ; 1 (1)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync                                                                                                                                          ;
;       |clock_0_out_arbitrator:the_clock_0_out|                                                  ; 2 (2)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_0_out_arbitrator:the_clock_0_out                                                                                                                                                                                                ;
;       |clock_1:the_clock_1|                                                                     ; 23 (1)            ; 136 (112)    ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1                                                                                                                                                                                                                   ;
;          |clock_1_edge_to_pulse:read_done_edge_to_pulse|                                        ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_edge_to_pulse:read_done_edge_to_pulse                                                                                                                                                                     ;
;          |clock_1_edge_to_pulse:read_request_edge_to_pulse|                                     ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_edge_to_pulse:read_request_edge_to_pulse                                                                                                                                                                  ;
;          |clock_1_edge_to_pulse:write_done_edge_to_pulse|                                       ; 0 (0)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_edge_to_pulse:write_done_edge_to_pulse                                                                                                                                                                    ;
;          |clock_1_edge_to_pulse:write_request_edge_to_pulse|                                    ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_edge_to_pulse:write_request_edge_to_pulse                                                                                                                                                                 ;
;          |clock_1_master_FSM:master_FSM|                                                        ; 9 (9)             ; 7 (7)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM                                                                                                                                                                                     ;
;          |clock_1_master_read_done_sync_module:clock_1_master_read_done_sync|                   ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync                                                                                                                                                ;
;          |clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|                 ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync                                                                                                                                              ;
;          |clock_1_slave_FSM:slave_FSM|                                                          ; 10 (10)           ; 5 (5)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM                                                                                                                                                                                       ;
;          |clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync|               ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync                                                                                                                                            ;
;          |clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync|             ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync                                                                                                                                          ;
;       |clock_1_in_arbitrator:the_clock_1_in|                                                    ; 6 (6)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1_in_arbitrator:the_clock_1_in                                                                                                                                                                                                  ;
;       |clock_1_out_arbitrator:the_clock_1_out|                                                  ; 2 (2)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1_out_arbitrator:the_clock_1_out                                                                                                                                                                                                ;
;       |cpu_0:the_cpu_0|                                                                         ; 1924 (1693)       ; 1510 (1332)  ; 70144       ; 0    ; 4            ; 0       ; 2         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0                                                                                                                                                                                                                       ;
;          |cpu_0_bht_module:cpu_0_bht|                                                           ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht                                                                                                                                                                                            ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram                                                                                                                                                                  ;
;                |altsyncram_q8e1:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated                                                                                                                                   ;
;                   |altsyncram_pfn1:altsyncram1|                                                 ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated|altsyncram_pfn1:altsyncram1                                                                                                       ;
;          |cpu_0_dc_data_module:cpu_0_dc_data|                                                   ; 0 (0)             ; 0 (0)        ; 16384       ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data                                                                                                                                                                                    ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 16384       ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram                                                                                                                                                          ;
;                |altsyncram_a422:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 16384       ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated                                                                                                                           ;
;          |cpu_0_dc_tag_module:cpu_0_dc_tag|                                                     ; 0 (0)             ; 0 (0)        ; 7680        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag                                                                                                                                                                                      ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 7680        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram                                                                                                                                                            ;
;                |altsyncram_vf22:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 7680        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_vf22:auto_generated                                                                                                                             ;
;          |cpu_0_ic_data_module:cpu_0_ic_data|                                                   ; 0 (0)             ; 0 (0)        ; 32768       ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data                                                                                                                                                                                    ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 32768       ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram                                                                                                                                                          ;
;                |altsyncram_cub1:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 32768       ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated                                                                                                                           ;
;                   |altsyncram_k1l1:altsyncram1|                                                 ; 0 (0)             ; 0 (0)        ; 32768       ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1                                                                                               ;
;          |cpu_0_ic_tag_module:cpu_0_ic_tag|                                                     ; 0 (0)             ; 0 (0)        ; 2560        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag                                                                                                                                                                                      ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 2560        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram                                                                                                                                                            ;
;                |altsyncram_tke1:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 2560        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_tke1:auto_generated                                                                                                                             ;
;          |cpu_0_mult_cell:the_cpu_0_mult_cell|                                                  ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 4            ; 0       ; 2         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell                                                                                                                                                                                   ;
;             |altmult_add:the_altmult_add_part_1|                                                ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1                                                                                                                                                ;
;                |mult_add_4cr2:auto_generated|                                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated                                                                                                                   ;
;                   |ded_mult_2o81:ded_mult1|                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1                                                                                           ;
;             |altmult_add:the_altmult_add_part_2|                                                ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2                                                                                                                                                ;
;                |mult_add_6cr2:auto_generated|                                                   ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated                                                                                                                   ;
;                   |ded_mult_2o81:ded_mult1|                                                     ; 0 (0)             ; 0 (0)        ; 0           ; 0    ; 2            ; 0       ; 1         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1                                                                                           ;
;          |cpu_0_nios2_oci:the_cpu_0_nios2_oci|                                                  ; 220 (5)           ; 178 (0)      ; 8192        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci                                                                                                                                                                                   ;
;             |cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|               ; 107 (0)           ; 90 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper                                                                                                               ;
;                |cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|                           ; 107 (107)         ; 90 (90)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1                                                          ;
;             |cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|                                 ; 10 (10)           ; 5 (5)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg                                                                                                                                 ;
;             |cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|                                   ; 33 (33)           ; 32 (32)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break                                                                                                                                   ;
;             |cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|                                   ; 11 (11)           ; 7 (7)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug                                                                                                                                   ;
;             |cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|                                         ; 54 (54)           ; 44 (44)      ; 8192        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem                                                                                                                                         ;
;                |cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component| ; 0 (0)             ; 0 (0)        ; 8192        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component                                                          ;
;                   |altsyncram:the_altsyncram|                                                   ; 0 (0)             ; 0 (0)        ; 8192        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram                                ;
;                      |altsyncram_c572:auto_generated|                                           ; 0 (0)             ; 0 (0)        ; 8192        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated ;
;          |cpu_0_register_bank_a_module:cpu_0_register_bank_a|                                   ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a                                                                                                                                                                    ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram                                                                                                                                          ;
;                |altsyncram_4be1:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_4be1:auto_generated                                                                                                           ;
;          |cpu_0_register_bank_b_module:cpu_0_register_bank_b|                                   ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b                                                                                                                                                                    ;
;             |altsyncram:the_altsyncram|                                                         ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram                                                                                                                                          ;
;                |altsyncram_5be1:auto_generated|                                                 ; 0 (0)             ; 0 (0)        ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_5be1:auto_generated                                                                                                           ;
;          |cpu_0_test_bench:the_cpu_0_test_bench|                                                ; 11 (11)           ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench                                                                                                                                                                                 ;
;       |cpu_0_data_master_arbitrator:the_cpu_0_data_master|                                      ; 262 (262)         ; 76 (76)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master                                                                                                                                                                                    ;
;       |cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|                        ; 135 (135)         ; 47 (47)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master                                                                                                                                                                      ;
;       |cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|                          ; 32 (32)           ; 3 (3)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module                                                                                                                                                                        ;
;       |jtag_uart_0:the_jtag_uart_0|                                                             ; 135 (41)          ; 106 (13)     ; 1024        ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0                                                                                                                                                                                                           ;
;          |alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|                                      ; 44 (44)           ; 53 (53)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic                                                                                                                                                           ;
;          |jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|                                        ; 25 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r                                                                                                                                                             ;
;             |scfifo:rfifo|                                                                      ; 25 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo                                                                                                                                                ;
;                |scfifo_1n21:auto_generated|                                                     ; 25 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated                                                                                                                     ;
;                   |a_dpfifo_8t21:dpfifo|                                                        ; 25 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo                                                                                                ;
;                      |a_fefifo_7cf:fifo_state|                                                  ; 13 (7)            ; 8 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state                                                                        ;
;                         |cntr_rj7:count_usedw|                                                  ; 6 (6)             ; 6 (6)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw                                                   ;
;                      |cntr_dl8:rd_ptr_count|                                                    ; 6 (6)             ; 6 (6)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_dl8:rd_ptr_count                                                                          ;
;                      |cntr_dl8:wr_ptr|                                                          ; 6 (6)             ; 6 (6)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_dl8:wr_ptr                                                                                ;
;                      |dpram_5h21:FIFOram|                                                       ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram                                                                             ;
;                         |altsyncram_9tl1:altsyncram2|                                           ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2                                                 ;
;          |jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|                                        ; 25 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w                                                                                                                                                             ;
;             |scfifo:wfifo|                                                                      ; 25 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo                                                                                                                                                ;
;                |scfifo_1n21:auto_generated|                                                     ; 25 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated                                                                                                                     ;
;                   |a_dpfifo_8t21:dpfifo|                                                        ; 25 (0)            ; 20 (0)       ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo                                                                                                ;
;                      |a_fefifo_7cf:fifo_state|                                                  ; 13 (7)            ; 8 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state                                                                        ;
;                         |cntr_rj7:count_usedw|                                                  ; 6 (6)             ; 6 (6)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw                                                   ;
;                      |cntr_dl8:rd_ptr_count|                                                    ; 6 (6)             ; 6 (6)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_dl8:rd_ptr_count                                                                          ;
;                      |cntr_dl8:wr_ptr|                                                          ; 6 (6)             ; 6 (6)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_dl8:wr_ptr                                                                                ;
;                      |dpram_5h21:FIFOram|                                                       ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram                                                                             ;
;                         |altsyncram_9tl1:altsyncram2|                                           ; 0 (0)             ; 0 (0)        ; 512         ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2                                                 ;
;       |jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave|              ; 2 (2)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave                                                                                                                                                            ;
;       |sdram_0:the_sdram_0|                                                                     ; 262 (212)         ; 238 (152)    ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0                                                                                                                                                                                                                   ;
;          |sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|                            ; 50 (50)           ; 86 (86)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module                                                                                                                                                         ;
;       |sdram_0_s1_arbitrator:the_sdram_0_s1|                                                    ; 102 (52)          ; 34 (3)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1                                                                                                                                                                                                  ;
;          |rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1| ; 25 (25)           ; 12 (12)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1                                                                                                             ;
;          |rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1| ; 25 (25)           ; 19 (19)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1                                                                                                             ;
;       |sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|                              ; 77 (77)           ; 14 (14)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0                                                                                                                                                                            ;
;       |system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch|            ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch                                                                                                                                                          ;
;       |system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|                  ; 0 (0)             ; 2 (2)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch                                                                                                                                                                ;
;       |timer_0:the_timer_0|                                                                     ; 115 (115)         ; 120 (120)    ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|timer_0:the_timer_0                                                                                                                                                                                                                   ;
;       |timer_0_s1_arbitrator:the_timer_0_s1|                                                    ; 1 (1)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|timer_0_s1_arbitrator:the_timer_0_s1                                                                                                                                                                                                  ;
;       |timer_1:the_timer_1|                                                                     ; 126 (126)         ; 120 (120)    ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|timer_1:the_timer_1                                                                                                                                                                                                                   ;
;       |timer_1_s1_arbitrator:the_timer_1_s1|                                                    ; 3 (3)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|timer_1_s1_arbitrator:the_timer_1_s1                                                                                                                                                                                                  ;
;       |tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|          ; 82 (82)           ; 62 (62)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_NIOS_DEVICE_LED|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave                                                                                                                                                        ;
+-------------------------------------------------------------------------------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                                                                                                                                                                               ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-----------------------------------+
; Name                                                                                                                                                                                                                                                         ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF                               ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-----------------------------------+
; I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_mj01:auto_generated|ALTSYNCRAM                                                                                                                                                                             ; AUTO ; ROM              ; 64           ; 16           ; --           ; --           ; 1024  ; DE2_NIOS_DEVICE_LED0.rtl.mif      ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated|altsyncram_pfn1:altsyncram1|ALTSYNCRAM                                                                                                       ; AUTO ; True Dual Port   ; 256          ; 2            ; 256          ; 2            ; 512   ; cpu_0_bht_ram.mif                 ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated|ALTSYNCRAM                                                                                                                           ; AUTO ; True Dual Port   ; 512          ; 32           ; 512          ; 32           ; 16384 ; None                              ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_vf22:auto_generated|ALTSYNCRAM                                                                                                                             ; AUTO ; True Dual Port   ; 512          ; 15           ; 512          ; 15           ; 7680  ; cpu_0_dc_tag_ram.mif              ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1|ALTSYNCRAM                                                                                               ; AUTO ; True Dual Port   ; 1024         ; 32           ; 1024         ; 32           ; 32768 ; None                              ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_tke1:auto_generated|ALTSYNCRAM                                                                                                                             ; AUTO ; Simple Dual Port ; 128          ; 20           ; 128          ; 20           ; 2560  ; cpu_0_ic_tag_ram.mif              ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port   ; 256          ; 32           ; 256          ; 32           ; 8192  ; cpu_0_ociram_default_contents.mif ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_4be1:auto_generated|ALTSYNCRAM                                                                                                           ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024  ; cpu_0_rf_ram_a.mif                ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_5be1:auto_generated|ALTSYNCRAM                                                                                                           ; AUTO ; Simple Dual Port ; 32           ; 32           ; 32           ; 32           ; 1024  ; cpu_0_rf_ram_b.mif                ;
; system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2|ALTSYNCRAM                                                 ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512   ; None                              ;
; system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2|ALTSYNCRAM                                                 ; AUTO ; Simple Dual Port ; 64           ; 8            ; 64           ; 8            ; 512   ; None                              ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+-----------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary        ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 0           ;
; Simple Multipliers (18-bit)           ; 2           ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 4           ;
; Signed Embedded Multipliers           ; 0           ;
; Unsigned Embedded Multipliers         ; 2           ;
; Mixed Sign Embedded Multipliers       ; 0           ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


+-------------------------------------------------------------------+
; State Machine - |DE2_NIOS_DEVICE_LED|I2C_AV_Config:u1|mSetup_ST   ;
+----------------+----------------+----------------+----------------+
; Name           ; mSetup_ST.0000 ; mSetup_ST.0010 ; mSetup_ST.0001 ;
+----------------+----------------+----------------+----------------+
; mSetup_ST.0000 ; 0              ; 0              ; 0              ;
; mSetup_ST.0001 ; 1              ; 0              ; 1              ;
; mSetup_ST.0010 ; 1              ; 1              ; 0              ;
+----------------+----------------+----------------+----------------+


+-------------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_state                    ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
; Name        ; i_state.101 ; i_state.111 ; i_state.001 ; i_state.011 ; i_state.010 ; i_state.000 ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
; i_state.000 ; 0           ; 0           ; 0           ; 0           ; 0           ; 0           ;
; i_state.010 ; 0           ; 0           ; 0           ; 0           ; 1           ; 1           ;
; i_state.011 ; 0           ; 0           ; 0           ; 1           ; 0           ; 1           ;
; i_state.001 ; 0           ; 0           ; 1           ; 0           ; 0           ; 1           ;
; i_state.111 ; 0           ; 1           ; 0           ; 0           ; 0           ; 1           ;
; i_state.101 ; 1           ; 0           ; 0           ; 0           ; 0           ; 1           ;
+-------------+-------------+-------------+-------------+-------------+-------------+-------------+


+-----------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_next ;
+------------+------------+------------+------------+-------------------------+
; Name       ; i_next.101 ; i_next.010 ; i_next.111 ; i_next.000              ;
+------------+------------+------------+------------+-------------------------+
; i_next.000 ; 0          ; 0          ; 0          ; 0                       ;
; i_next.111 ; 0          ; 0          ; 1          ; 1                       ;
; i_next.010 ; 0          ; 1          ; 0          ; 1                       ;
; i_next.101 ; 1          ; 0          ; 0          ; 1                       ;
+------------+------------+------------+------------+-------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_state                                                                                                                          ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; Name              ; m_state.100000000 ; m_state.010000000 ; m_state.001000000 ; m_state.000100000 ; m_state.000010000 ; m_state.000001000 ; m_state.000000100 ; m_state.000000010 ; m_state.000000001 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; m_state.000000001 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ;
; m_state.000100000 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.000010000 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.000001000 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 1                 ;
; m_state.100000000 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.000000100 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 1                 ;
; m_state.000000010 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 1                 ;
; m_state.001000000 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; m_state.010000000 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+


+----------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_next                  ;
+------------------+------------------+------------------+------------------+------------------+
; Name             ; m_next.010000000 ; m_next.000010000 ; m_next.000001000 ; m_next.000000001 ;
+------------------+------------------+------------------+------------------+------------------+
; m_next.000000001 ; 0                ; 0                ; 0                ; 0                ;
; m_next.000001000 ; 0                ; 0                ; 1                ; 1                ;
; m_next.010000000 ; 1                ; 0                ; 0                ; 1                ;
; m_next.000010000 ; 0                ; 1                ; 0                ; 1                ;
+------------------+------------------+------------------+------------------+------------------+


+-----------------------------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state ;
+------------------+------------------+------------------+--------------------------------------------------------+
; Name             ; master_state.100 ; master_state.010 ; master_state.001                                       ;
+------------------+------------------+------------------+--------------------------------------------------------+
; master_state.001 ; 0                ; 0                ; 0                                                      ;
; master_state.100 ; 1                ; 0                ; 1                                                      ;
; master_state.010 ; 0                ; 1                ; 1                                                      ;
+------------------+------------------+------------------+--------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state ;
+-----------------+-----------------+-----------------+--------------------------------------------------------+
; Name            ; slave_state.100 ; slave_state.010 ; slave_state.001                                        ;
+-----------------+-----------------+-----------------+--------------------------------------------------------+
; slave_state.001 ; 0               ; 0               ; 0                                                      ;
; slave_state.010 ; 0               ; 1               ; 1                                                      ;
; slave_state.100 ; 1               ; 0               ; 1                                                      ;
+-----------------+-----------------+-----------------+--------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state ;
+------------------+------------------+------------------+--------------------------------------------------------+
; Name             ; master_state.100 ; master_state.010 ; master_state.001                                       ;
+------------------+------------------+------------------+--------------------------------------------------------+
; master_state.001 ; 0                ; 0                ; 0                                                      ;
; master_state.100 ; 1                ; 0                ; 1                                                      ;
; master_state.010 ; 0                ; 1                ; 1                                                      ;
+------------------+------------------+------------------+--------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state ;
+-----------------+-----------------+-----------------+--------------------------------------------------------+
; Name            ; slave_state.100 ; slave_state.010 ; slave_state.001                                        ;
+-----------------+-----------------+-----------------+--------------------------------------------------------+
; slave_state.001 ; 0               ; 0               ; 0                                                      ;
; slave_state.010 ; 0               ; 1               ; 1                                                      ;
; slave_state.100 ; 1               ; 0               ; 1                                                      ;
+-----------------+-----------------+-----------------+--------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize ;
+------------+------------+------------+------------+------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name       ; DRsize.011 ; DRsize.100 ; DRsize.101 ; DRsize.010 ; DRsize.001 ; DRsize.000                                                                                                                                             ;
+------------+------------+------------+------------+------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; DRsize.000 ; 0          ; 0          ; 0          ; 0          ; 0          ; 0                                                                                                                                                      ;
; DRsize.001 ; 0          ; 0          ; 0          ; 0          ; 1          ; 1                                                                                                                                                      ;
; DRsize.010 ; 0          ; 0          ; 0          ; 1          ; 0          ; 1                                                                                                                                                      ;
; DRsize.101 ; 0          ; 0          ; 1          ; 0          ; 0          ; 1                                                                                                                                                      ;
; DRsize.100 ; 0          ; 1          ; 0          ; 0          ; 0          ; 1                                                                                                                                                      ;
; DRsize.011 ; 1          ; 0          ; 0          ; 0          ; 0          ; 1                                                                                                                                                      ;
+------------+------------+------------+------------+------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name                                                                                                       ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+---------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_out                         ; yes                                                              ; yes                                        ;
; system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch|data_out                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_out         ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|data_out       ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync|data_out         ; yes                                                              ; yes                                        ;
; system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_in_d1                       ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[9]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[9]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[22]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[22]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[10]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[10]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[11]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[11]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[12]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[12]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[13]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[13]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[14]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[14]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[15]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[15]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[16]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[16]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[17]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[17]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[18]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[18]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[19]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[19]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[20]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[20]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[21]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[21]                                                                  ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[1]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[1]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch|data_in_d1                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[2]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[2]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[3]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[3]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[4]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[4]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[5]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[5]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[6]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[6]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[7]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[7]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_address[8]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_address[8]                                                                   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_byteenable[0]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_byteenable[0]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_byteenable[1]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_byteenable[1]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync|data_in_d1       ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|data_in_d1     ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync|data_in_d1       ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_out     ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_out   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync|data_out     ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync|data_out   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[9]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[9]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[22]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[22]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[10]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[10]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[11]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[11]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[12]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[12]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[13]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[13]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[14]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[14]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[15]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[15]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[16]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[16]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[17]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[17]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[18]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[18]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[19]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[19]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[20]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[20]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[21]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[21]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[1]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[1]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[2]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[2]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[3]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[3]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[4]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[4]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[5]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[5]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[6]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[6]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[7]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[7]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_address_d1[8]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_address_d1[8]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_byteenable_d1[0]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_byteenable_d1[0]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_byteenable_d1[1]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_byteenable_d1[1]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync|data_in_d1   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync|data_in_d1 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync|data_in_d1   ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync|data_in_d1 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[0]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[0]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[1]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[1]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[2]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[2]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[3]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[3]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[4]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[4]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[5]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[5]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[6]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[6]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[7]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[7]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[8]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[8]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[9]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[9]                                                                 ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[10]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[10]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[11]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[11]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[12]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[12]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[13]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[13]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[14]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[14]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|master_writedata[15]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|master_writedata[15]                                                                ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[0]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[0]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[1]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[1]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[2]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[2]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[3]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[3]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[4]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[4]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[5]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[5]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[6]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[6]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[7]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[7]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[8]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[8]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[9]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[9]                                                               ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[10]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[10]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[11]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[11]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[12]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[12]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[13]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[13]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[14]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[14]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_1:the_clock_1|slave_writedata_d1[15]                                                              ; yes                                                              ; yes                                        ;
; system_0:u0|clock_0:the_clock_0|slave_writedata_d1[15]                                                              ; yes                                                              ; yes                                        ;
+---------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+


+-------------------------------------------------------------+
; Logic Cells Representing Combinational Loops                ;
+--------------------------------------------------------+----+
; Logic Cell Name                                        ;    ;
+--------------------------------------------------------+----+
; rtl~0                                                  ;    ;
; rtl~1                                                  ;    ;
; rtl~2                                                  ;    ;
; rtl~3                                                  ;    ;
; rtl~4                                                  ;    ;
; rtl~5                                                  ;    ;
; rtl~6                                                  ;    ;
; rtl~7                                                  ;    ;
; rtl~8                                                  ;    ;
; rtl~9                                                  ;    ;
; Number of logic cells representing combinational loops ; 10 ;
+--------------------------------------------------------+----+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 2770  ;
; Number of registers using Synchronous Clear  ; 79    ;
; Number of registers using Synchronous Load   ; 319   ;
; Number of registers using Asynchronous Clear ; 2532  ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 1828  ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                                         ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                                          ; Fan out ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; system_0:u0|sdram_0:the_sdram_0|m_cmd[0]                                                                                                                   ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|m_cmd[1]                                                                                                                   ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|m_cmd[2]                                                                                                                   ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|m_cmd[3]                                                                                                                   ; 1       ;
; system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|write_n_to_the_cfi_flash_0                                      ; 1       ;
; system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn                                        ; 1       ;
; system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|select_n_to_the_cfi_flash_0                                     ; 1       ;
; system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|sram_0_avalon_slave_0_arb_addend[0]                                                 ; 6       ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[0]                                                                                                           ; 19      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[2]                                                                                                           ; 15      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[3]                                                                                                           ; 21      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1]                                                                                                           ; 16      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[4]                                                                                                           ; 11      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[5]                                                                                                           ; 12      ;
; I2C_AV_Config:u1|I2C_Controller:u0|SCLK                                                                                                                    ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|i_addr[11]                                                                                                                 ; 10      ;
; system_0:u0|sdram_0:the_sdram_0|i_cmd[0]                                                                                                                   ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|i_cmd[1]                                                                                                                   ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|i_cmd[2]                                                                                                                   ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|i_cmd[3]                                                                                                                   ; 2       ;
; system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0]                   ; 6       ;
; system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_waitrequest                                                               ; 17      ;
; system_0:u0|cpu_0:the_cpu_0|M_pipe_flush                                                                                                                   ; 41      ;
; system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[0]                                           ; 5       ;
; sld_hub:sld_hub_inst|hub_tdo                                                                                                                               ; 2       ;
; system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|fifo_contains_ones_n ; 3       ;
; system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|fifo_contains_ones_n ; 3       ;
; system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_addend[0]                                                                                  ; 5       ;
; system_0:u0|sdram_0:the_sdram_0|refresh_counter[3]                                                                                                         ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|refresh_counter[12]                                                                                                        ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|refresh_counter[9]                                                                                                         ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|refresh_counter[8]                                                                                                         ; 2       ;
; system_0:u0|sdram_0:the_sdram_0|refresh_counter[7]                                                                                                         ; 2       ;
; system_0:u0|jtag_uart_0:the_jtag_uart_0|av_waitrequest                                                                                                     ; 1       ;
; system_0:u0|cpu_0:the_cpu_0|hbreak_enabled                                                                                                                 ; 12      ;
; I2C_AV_Config:u1|I2C_Controller:u0|END                                                                                                                     ; 5       ;
; I2C_AV_Config:u1|I2C_Controller:u0|SDO                                                                                                                     ; 4       ;
; system_0:u0|cpu_0:the_cpu_0|ic_tag_clr_valid_bits                                                                                                          ; 1       ;
; system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[20]                                                                                                         ; 1       ;
; system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[9]                                                           ; 11      ;
; system_0:u0|jtag_uart_0:the_jtag_uart_0|t_dav                                                                                                              ; 3       ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[5]                           ; 2       ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[4]                           ; 2       ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[3]                           ; 2       ;
; system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[1]                           ; 2       ;
; system_0:u0|cpu_0:the_cpu_0|A_wr_dst_reg_from_M                                                                                                            ; 66      ;
; system_0:u0|timer_1:the_timer_1|internal_counter[0]                                                                                                        ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[1]                                                                                                        ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[2]                                                                                                        ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[3]                                                                                                        ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[4]                                                                                                        ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[7]                                                                                                        ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[9]                                                                                                        ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[10]                                                                                                       ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[15]                                                                                                       ; 3       ;
; system_0:u0|timer_1:the_timer_1|internal_counter[16]                                                                                                       ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[0]                                                                                                        ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[1]                                                                                                        ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[2]                                                                                                        ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[3]                                                                                                        ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[4]                                                                                                        ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[7]                                                                                                        ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[9]                                                                                                        ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[10]                                                                                                       ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[15]                                                                                                       ; 3       ;
; system_0:u0|timer_0:the_timer_0|internal_counter[16]                                                                                                       ; 3       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[0]                                                                                                       ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[1]                                                                                                       ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[2]                                                                                                       ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[3]                                                                                                       ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[4]                                                                                                       ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[7]                                                                                                       ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[9]                                                                                                       ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[10]                                                                                                      ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_l_register[15]                                                                                                      ; 2       ;
; system_0:u0|timer_1:the_timer_1|period_h_register[0]                                                                                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[0]                                                                                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[1]                                                                                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[2]                                                                                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[3]                                                                                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[4]                                                                                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[7]                                                                                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[9]                                                                                                       ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[10]                                                                                                      ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_l_register[15]                                                                                                      ; 2       ;
; system_0:u0|timer_0:the_timer_0|period_h_register[0]                                                                                                       ; 2       ;
; Total number of inverted registers = 86                                                                                                                    ;         ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                                                                     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|ic_tag_wraddress[1]                                                                                                                                                 ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|A_slow_inst_result[2]                                                                                                                                               ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|D_iw[18]                                                                                                                                                            ;
; 3:1                ; 18 bits   ; 36 LEs        ; 36 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|D_iw[23]                                                                                                                                                            ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|A_inst_result[1]                                                                                                                                                    ;
; 3:1                ; 27 bits   ; 54 LEs        ; 54 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|A_inst_result[20]                                                                                                                                                   ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|M_st_data[16]                                                                                                                                                       ;
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|M_st_data[31]                                                                                                                                                       ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_cnt[3]                                                                                                                                                   ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|ic_fill_ap_offset[2]                                                                                                                                                ;
; 5:1                ; 2 bits    ; 6 LEs         ; 2 LEs                ; 4 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|entries[0]                                                                                            ;
; 4:1                ; 19 bits   ; 38 LEs        ; 38 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[20]                                                                           ;
; 4:1                ; 11 bits   ; 22 LEs        ; 22 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonDReg[3]                                                                            ;
; 4:1                ; 9 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|MonAReg[7]                                                                            ;
; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2]                                                                                                                                                        ;
; 4:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|E_src2[11]                                                                                                                                                          ;
; 8:1                ; 4 bits    ; 20 LEs        ; 8 LEs                ; 12 LEs                 ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|E_control_rd_data_without_mmu_regs[1]                                                                                                                               ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[1]                                                                       ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[0]                                                                       ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|sram_0_avalon_slave_0_wait_counter[0]                                                                                    ;
; 5:1                ; 32 bits   ; 96 LEs        ; 32 LEs               ; 64 LEs                 ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|break_readreg[23]                                                               ;
; 5:1                ; 21 bits   ; 63 LEs        ; 63 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|M_pipe_flush_waddr[4]                                                                                                                                               ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|M_mem_byte_en[2]                                                                                                                                                    ;
; 5:1                ; 15 bits   ; 45 LEs        ; 30 LEs               ; 15 LEs                 ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|E_src2[25]                                                                                                                                                          ;
; 5:1                ; 32 bits   ; 96 LEs        ; 96 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|E_src1[11]                                                                                                                                                          ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; Yes        ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[2]                                                                                                                                    ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_bank[1]                                                                                                                                                       ;
; 6:1                ; 12 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|F_pc[10]                                                                                                                                                            ;
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_count[0]                                                                                                                                                      ;
; 6:1                ; 4 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_addr[8]                                                                                                                                                       ;
; 7:1                ; 2 bits    ; 8 LEs         ; 6 LEs                ; 2 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_addr[5]                                                                                                                                                       ;
; 7:1                ; 6 bits    ; 24 LEs        ; 18 LEs               ; 6 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_addr[0]                                                                                                                                                       ;
; 28:1               ; 4 bits    ; 72 LEs        ; 48 LEs               ; 24 LEs                 ; Yes        ; |DE2_NIOS_DEVICE_LED|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[1]                                                                                                                                         ;
; 12:1               ; 41 bits   ; 328 LEs       ; 0 LEs                ; 328 LEs                ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|active_data[12]                                                                                                                                                 ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_outgoing_tri_state_bridge_0_data[0]                                                               ;
; 4:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_data[2]                                                                                                                                                       ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|sram_0_avalon_slave_0_arb_share_counter_next_value[1]                                                                    ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cfgdout[2]                                                                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|readdata[0]                                                                                                                     ;
; 3:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_counter_next_value[2]                                      ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_share_counter_next_value[1]                                                              ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|F_iw[5]                                                                                                                                                             ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|F_iw[0]                                                                                                                                                             ;
; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|dc_data_portb_byte_en[0]                                                                                                                                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|Selector3                                                                                                                           ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_share_set_values[2]                                              ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|comb~3                                                                                                                                                          ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|updated_one_count~18                                      ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|updated_one_count~16                                      ;
; 4:1                ; 32 bits   ; 64 LEs        ; 64 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|E_logic_result[23]                                                                                                                                                  ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|D_dst_regnum[3]                                                                                                                                                     ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|E_alu_result[1]                                                                                                                                                     ;
; 4:1                ; 9 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|E_alu_result[6]                                                                                                                                                     ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|readdata[4]                                                                                                                     ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|readdata[1]                                                                                                                     ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|Selector3                                                                                                                           ;
; 5:1                ; 7 bits    ; 21 LEs        ; 21 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|E_alu_result[27]                                                                                                                                                    ;
; 5:1                ; 13 bits   ; 39 LEs        ; 39 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|E_alu_result[20]                                                                                                                                                    ;
; 5:1                ; 32 bits   ; 96 LEs        ; 96 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|D_src2_reg[0]                                                                                                                                                       ;
; 5:1                ; 16 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[29]                                                                                                                                            ;
; 5:1                ; 8 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[13]                                                                                                                                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|A_wr_data_unfiltered[5]                                                                                                                                             ;
; 6:1                ; 10 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|F_ic_tag_rd_addr_nxt[2]                                                                                                                                             ;
; 11:1               ; 2 bits    ; 14 LEs        ; 4 LEs                ; 10 LEs                 ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|Selector34                                                                                                                                                      ;
; 12:1               ; 2 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|Selector24                                                                                                                                                      ;
; 16:1               ; 2 bits    ; 20 LEs        ; 8 LEs                ; 12 LEs                 ; No         ; |DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|Selector26                                                                                                                                                      ;
; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[36] ;
; 6:1                ; 6 bits    ; 24 LEs        ; 18 LEs               ; 6 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12] ;
; 6:1                ; 18 bits   ; 72 LEs        ; 36 LEs               ; 36 LEs                 ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[21] ;
; 6:1                ; 7 bits    ; 28 LEs        ; 21 LEs               ; 7 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[4]  ;
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|count[1]                                                                                                ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[9]                                                                                             ;
; 5:1                ; 3 bits    ; 9 LEs         ; 6 LEs                ; 3 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[7]                                                                                             ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |DE2_NIOS_DEVICE_LED|system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[1]                                                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_0:the_clock_0                                 ;
+-------------------+-------+----------------------------+-------------------------------+
; Assignment        ; Value ; From                       ; To                            ;
+-------------------+-------+----------------------------+-------------------------------+
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[22]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[21]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[20]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[19]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[18]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[17]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[16]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[15]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[14]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[13]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[12]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[11]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[10]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[9]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[8]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[7]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[6]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[5]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[4]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[3]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[2]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[1]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[0]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[1]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[0]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[21]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[20]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[19]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[18]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[17]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[16]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[15]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[14]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[13]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[12]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[11]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[10]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[9]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[8]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[7]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[6]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[5]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[4]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[3]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[2]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[1]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[0]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[15]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[14]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[13]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[12]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[11]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[10]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[9]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[8]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[7]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[6]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[5]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[4]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[3]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[2]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[1]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[0]           ;
; CUT               ; ON    ; *                          ; slave_readdata[15]            ;
; CUT               ; ON    ; *                          ; slave_readdata[14]            ;
; CUT               ; ON    ; *                          ; slave_readdata[13]            ;
; CUT               ; ON    ; *                          ; slave_readdata[12]            ;
; CUT               ; ON    ; *                          ; slave_readdata[11]            ;
; CUT               ; ON    ; *                          ; slave_readdata[10]            ;
; CUT               ; ON    ; *                          ; slave_readdata[9]             ;
; CUT               ; ON    ; *                          ; slave_readdata[8]             ;
; CUT               ; ON    ; *                          ; slave_readdata[7]             ;
; CUT               ; ON    ; *                          ; slave_readdata[6]             ;
; CUT               ; ON    ; *                          ; slave_readdata[5]             ;
; CUT               ; ON    ; *                          ; slave_readdata[4]             ;
; CUT               ; ON    ; *                          ; slave_readdata[3]             ;
; CUT               ; ON    ; *                          ; slave_readdata[2]             ;
; CUT               ; ON    ; *                          ; slave_readdata[1]             ;
; CUT               ; ON    ; *                          ; slave_readdata[0]             ;
; CUT               ; ON    ; *                          ; slave_readdata[15]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[14]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[13]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[12]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[11]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[10]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[9]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[8]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[7]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[6]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[5]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[4]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[3]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[2]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[1]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[0]~reg0        ;
; CUT               ; ON    ; slave_writedata_d1[15]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[15]        ;
; CUT               ; ON    ; slave_writedata_d1[14]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[14]        ;
; CUT               ; ON    ; slave_writedata_d1[13]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[13]        ;
; CUT               ; ON    ; slave_writedata_d1[12]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[12]        ;
; CUT               ; ON    ; slave_writedata_d1[11]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[11]        ;
; CUT               ; ON    ; slave_writedata_d1[10]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[10]        ;
; CUT               ; ON    ; slave_writedata_d1[9]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[9]         ;
; CUT               ; ON    ; slave_writedata_d1[8]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[8]         ;
; CUT               ; ON    ; slave_writedata_d1[7]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[7]         ;
; CUT               ; ON    ; slave_writedata_d1[6]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[6]         ;
; CUT               ; ON    ; slave_writedata_d1[5]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[5]         ;
; CUT               ; ON    ; slave_writedata_d1[4]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[4]         ;
; CUT               ; ON    ; slave_writedata_d1[3]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[3]         ;
; CUT               ; ON    ; slave_writedata_d1[2]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[2]         ;
; CUT               ; ON    ; slave_writedata_d1[1]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[1]         ;
; CUT               ; ON    ; slave_writedata_d1[0]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[0]         ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[15]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[14]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[13]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[12]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[11]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[10]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[9]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[8]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[7]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[6]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[5]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[4]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[3]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[2]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[1]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[0]~reg0      ;
; CUT               ; ON    ; slave_address_d1[22]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[22]          ;
; CUT               ; ON    ; slave_address_d1[21]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[21]          ;
; CUT               ; ON    ; slave_address_d1[20]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[20]          ;
; CUT               ; ON    ; slave_address_d1[19]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[19]          ;
; CUT               ; ON    ; slave_address_d1[18]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[18]          ;
; CUT               ; ON    ; slave_address_d1[17]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[17]          ;
; CUT               ; ON    ; slave_address_d1[16]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[16]          ;
; CUT               ; ON    ; slave_address_d1[15]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[15]          ;
; CUT               ; ON    ; slave_address_d1[14]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[14]          ;
; CUT               ; ON    ; slave_address_d1[13]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[13]          ;
; CUT               ; ON    ; slave_address_d1[12]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[12]          ;
; CUT               ; ON    ; slave_address_d1[11]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[11]          ;
; CUT               ; ON    ; slave_address_d1[10]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[10]          ;
; CUT               ; ON    ; slave_address_d1[9]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[9]           ;
; CUT               ; ON    ; slave_address_d1[8]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[8]           ;
; CUT               ; ON    ; slave_address_d1[7]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[7]           ;
; CUT               ; ON    ; slave_address_d1[6]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[6]           ;
; CUT               ; ON    ; slave_address_d1[5]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[5]           ;
; CUT               ; ON    ; slave_address_d1[4]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[4]           ;
; CUT               ; ON    ; slave_address_d1[3]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[3]           ;
; CUT               ; ON    ; slave_address_d1[2]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[2]           ;
; CUT               ; ON    ; slave_address_d1[1]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[1]           ;
; CUT               ; ON    ; slave_address_d1[0]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[0]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[22]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[21]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[20]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[19]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[18]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[17]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[16]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[15]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[14]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[13]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[12]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[11]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[10]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[9]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[8]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[7]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[6]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[5]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[4]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[3]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[2]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[1]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[0]~reg0        ;
; CUT               ; ON    ; slave_nativeaddress_d1[21] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[21]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[20] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[20]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[19] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[19]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[18] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[18]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[17] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[17]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[16] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[16]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[15] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[15]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[14] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[14]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[13] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[13]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[12] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[12]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[11] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[11]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[10] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[10]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[9]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[9]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[8]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[8]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[7]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[7]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[6]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[6]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[5]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[5]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[4]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[4]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[3]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[3]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[2]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[2]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[1]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[1]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[0]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[0]     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[21]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[20]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[19]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[18]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[17]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[16]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[15]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[14]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[13]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[12]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[11]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[10]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[9]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[8]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[7]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[6]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[5]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[4]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[3]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[2]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[1]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[0]~reg0  ;
; CUT               ; ON    ; slave_byteenable_d1[1]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_byteenable_d1[1]        ;
; CUT               ; ON    ; slave_byteenable_d1[0]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_byteenable_d1[0]        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[1]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[0]~reg0     ;
+-------------------+-------+----------------------------+-------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync ;
+-------------------+-------+------+----------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                     ;
+-------------------+-------+------+----------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                          ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                             ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                             ;
+-------------------+-------+------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync ;
+-------------------+-------+------+------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                       ;
+-------------------+-------+------+------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                 ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                            ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                               ;
+-------------------+-------+------+------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                         ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                   ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                              ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                                 ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                                 ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                           ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                     ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                                ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                                   ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                                   ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_0:the_clock_0|clock_0_bit_pipe:endofpacket_bit_pipe ;
+-------------------+-------+------------+-----------------------------------------------------+
; Assignment        ; Value ; From       ; To                                                  ;
+-------------------+-------+------------+-----------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -          ; data_out                                            ;
; PRESERVE_REGISTER ; ON    ; -          ; data_out~reg0                                       ;
; CUT               ; ON    ; data_in_d1 ; *                                                   ;
; PRESERVE_REGISTER ; ON    ; -          ; data_in_d1                                          ;
+-------------------+-------+------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_1:the_clock_1                                 ;
+-------------------+-------+----------------------------+-------------------------------+
; Assignment        ; Value ; From                       ; To                            ;
+-------------------+-------+----------------------------+-------------------------------+
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[22]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[21]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[20]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[19]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[18]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[17]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[16]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[15]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[14]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[13]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[12]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[11]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[10]            ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[9]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[8]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[7]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[6]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[5]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[4]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[3]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[2]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[1]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[0]             ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[1]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[0]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[21]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[20]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[19]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[18]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[17]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[16]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[15]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[14]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[13]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[12]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[11]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[10]      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[9]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[8]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[7]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[6]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[5]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[4]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[3]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[2]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[1]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[0]       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[15]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[14]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[13]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[12]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[11]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[10]          ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[9]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[8]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[7]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[6]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[5]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[4]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[3]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[2]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[1]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[0]           ;
; CUT               ; ON    ; *                          ; slave_readdata[15]            ;
; CUT               ; ON    ; *                          ; slave_readdata[14]            ;
; CUT               ; ON    ; *                          ; slave_readdata[13]            ;
; CUT               ; ON    ; *                          ; slave_readdata[12]            ;
; CUT               ; ON    ; *                          ; slave_readdata[11]            ;
; CUT               ; ON    ; *                          ; slave_readdata[10]            ;
; CUT               ; ON    ; *                          ; slave_readdata[9]             ;
; CUT               ; ON    ; *                          ; slave_readdata[8]             ;
; CUT               ; ON    ; *                          ; slave_readdata[7]             ;
; CUT               ; ON    ; *                          ; slave_readdata[6]             ;
; CUT               ; ON    ; *                          ; slave_readdata[5]             ;
; CUT               ; ON    ; *                          ; slave_readdata[4]             ;
; CUT               ; ON    ; *                          ; slave_readdata[3]             ;
; CUT               ; ON    ; *                          ; slave_readdata[2]             ;
; CUT               ; ON    ; *                          ; slave_readdata[1]             ;
; CUT               ; ON    ; *                          ; slave_readdata[0]             ;
; CUT               ; ON    ; *                          ; slave_readdata[15]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[14]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[13]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[12]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[11]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[10]~reg0       ;
; CUT               ; ON    ; *                          ; slave_readdata[9]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[8]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[7]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[6]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[5]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[4]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[3]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[2]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[1]~reg0        ;
; CUT               ; ON    ; *                          ; slave_readdata[0]~reg0        ;
; CUT               ; ON    ; slave_writedata_d1[15]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[15]        ;
; CUT               ; ON    ; slave_writedata_d1[14]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[14]        ;
; CUT               ; ON    ; slave_writedata_d1[13]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[13]        ;
; CUT               ; ON    ; slave_writedata_d1[12]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[12]        ;
; CUT               ; ON    ; slave_writedata_d1[11]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[11]        ;
; CUT               ; ON    ; slave_writedata_d1[10]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[10]        ;
; CUT               ; ON    ; slave_writedata_d1[9]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[9]         ;
; CUT               ; ON    ; slave_writedata_d1[8]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[8]         ;
; CUT               ; ON    ; slave_writedata_d1[7]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[7]         ;
; CUT               ; ON    ; slave_writedata_d1[6]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[6]         ;
; CUT               ; ON    ; slave_writedata_d1[5]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[5]         ;
; CUT               ; ON    ; slave_writedata_d1[4]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[4]         ;
; CUT               ; ON    ; slave_writedata_d1[3]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[3]         ;
; CUT               ; ON    ; slave_writedata_d1[2]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[2]         ;
; CUT               ; ON    ; slave_writedata_d1[1]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[1]         ;
; CUT               ; ON    ; slave_writedata_d1[0]      ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_writedata_d1[0]         ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[15]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[14]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[13]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[12]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[11]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[10]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[9]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[8]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[7]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[6]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[5]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[4]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[3]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[2]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[1]~reg0      ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_writedata[0]~reg0      ;
; CUT               ; ON    ; slave_address_d1[22]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[22]          ;
; CUT               ; ON    ; slave_address_d1[21]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[21]          ;
; CUT               ; ON    ; slave_address_d1[20]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[20]          ;
; CUT               ; ON    ; slave_address_d1[19]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[19]          ;
; CUT               ; ON    ; slave_address_d1[18]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[18]          ;
; CUT               ; ON    ; slave_address_d1[17]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[17]          ;
; CUT               ; ON    ; slave_address_d1[16]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[16]          ;
; CUT               ; ON    ; slave_address_d1[15]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[15]          ;
; CUT               ; ON    ; slave_address_d1[14]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[14]          ;
; CUT               ; ON    ; slave_address_d1[13]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[13]          ;
; CUT               ; ON    ; slave_address_d1[12]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[12]          ;
; CUT               ; ON    ; slave_address_d1[11]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[11]          ;
; CUT               ; ON    ; slave_address_d1[10]       ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[10]          ;
; CUT               ; ON    ; slave_address_d1[9]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[9]           ;
; CUT               ; ON    ; slave_address_d1[8]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[8]           ;
; CUT               ; ON    ; slave_address_d1[7]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[7]           ;
; CUT               ; ON    ; slave_address_d1[6]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[6]           ;
; CUT               ; ON    ; slave_address_d1[5]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[5]           ;
; CUT               ; ON    ; slave_address_d1[4]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[4]           ;
; CUT               ; ON    ; slave_address_d1[3]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[3]           ;
; CUT               ; ON    ; slave_address_d1[2]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[2]           ;
; CUT               ; ON    ; slave_address_d1[1]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[1]           ;
; CUT               ; ON    ; slave_address_d1[0]        ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_address_d1[0]           ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[22]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[21]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[20]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[19]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[18]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[17]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[16]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[15]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[14]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[13]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[12]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[11]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[10]~reg0       ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[9]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[8]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[7]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[6]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[5]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[4]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[3]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[2]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[1]~reg0        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_address[0]~reg0        ;
; CUT               ; ON    ; slave_nativeaddress_d1[21] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[21]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[20] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[20]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[19] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[19]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[18] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[18]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[17] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[17]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[16] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[16]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[15] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[15]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[14] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[14]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[13] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[13]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[12] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[12]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[11] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[11]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[10] ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[10]    ;
; CUT               ; ON    ; slave_nativeaddress_d1[9]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[9]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[8]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[8]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[7]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[7]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[6]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[6]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[5]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[5]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[4]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[4]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[3]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[3]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[2]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[2]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[1]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[1]     ;
; CUT               ; ON    ; slave_nativeaddress_d1[0]  ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_nativeaddress_d1[0]     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[21]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[20]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[19]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[18]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[17]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[16]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[15]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[14]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[13]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[12]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[11]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[10]~reg0 ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[9]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[8]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[7]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[6]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[5]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[4]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[3]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[2]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[1]~reg0  ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_nativeaddress[0]~reg0  ;
; CUT               ; ON    ; slave_byteenable_d1[1]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_byteenable_d1[1]        ;
; CUT               ; ON    ; slave_byteenable_d1[0]     ; *                             ;
; PRESERVE_REGISTER ; ON    ; -                          ; slave_byteenable_d1[0]        ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[1]~reg0     ;
; PRESERVE_REGISTER ; ON    ; -                          ; master_byteenable[0]~reg0     ;
+-------------------+-------+----------------------------+-------------------------------+


+---------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync ;
+-------------------+-------+------+----------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                     ;
+-------------------+-------+------+----------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                          ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                             ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                             ;
+-------------------+-------+------+----------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync ;
+-------------------+-------+------+------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                       ;
+-------------------+-------+------+------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                 ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                            ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                               ;
+-------------------+-------+------+------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                         ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                   ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                              ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                                 ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                                 ;
+-------------------+-------+------+--------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                                           ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                                     ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                                ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                                   ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                                   ;
+-------------------+-------+------+----------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|clock_1:the_clock_1|clock_1_bit_pipe:endofpacket_bit_pipe ;
+-------------------+-------+------------+-----------------------------------------------------+
; Assignment        ; Value ; From       ; To                                                  ;
+-------------------+-------+------------+-----------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -          ; data_out                                            ;
; PRESERVE_REGISTER ; ON    ; -          ; data_out~reg0                                       ;
; CUT               ; ON    ; data_in_d1 ; *                                                   ;
; PRESERVE_REGISTER ; ON    ; -          ; data_in_d1                                          ;
+-------------------+-------+------------+-----------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                               ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1 ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                           ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                            ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_tke1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                             ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                              ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                       ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                        ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated|altsyncram_pfn1:altsyncram1 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                   ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                    ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_4be1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                               ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_5be1:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                               ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_vf22:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                             ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                              ;
+---------------------------------+--------------------+------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                               ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                   ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                    ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                                                                                                                   ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -                                                                                                                                                    ;
+---------------------------------+-------+------+------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                         ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                          ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                                                                             ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                                                                              ;
+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                         ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                          ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2 ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                                                                                                         ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                                                                                                          ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------+
; Source assignments for system_0:u0|sdram_0:the_sdram_0        ;
+-----------------------------+-------+------+------------------+
; Assignment                  ; Value ; From ; To               ;
+-----------------------------+-------+------+------------------+
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[15]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[14]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[13]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[12]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[11]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[10]      ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[9]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[8]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[7]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[6]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[5]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[4]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[3]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[2]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[1]       ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[0]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_bank[1]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_bank[0]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[11]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[10]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[9]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[8]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[7]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[6]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[5]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[4]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[3]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[2]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[1]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_addr[0]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[15]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[15]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[14]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[14]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[13]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[13]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[12]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[12]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[11]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[11]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[10]       ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[10]       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[9]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[9]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[8]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[8]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[7]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[7]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[6]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[6]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[5]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[5]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[4]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[4]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[3]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[3]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[2]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[2]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[1]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[1]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_data[0]        ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; m_data[0]        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_dqm[1]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_dqm[0]         ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; oe               ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[15]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[14]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[13]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[12]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[11]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[10]~reg0 ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[9]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[8]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[7]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[6]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[5]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[4]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[3]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[2]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[1]~reg0  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; za_data[0]~reg0  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[3]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[2]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[1]         ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; m_cmd[0]         ;
+-----------------------------+-------+------+------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave ;
+-----------------------------+-------+------+----------------------------------------------------------------------+
; Assignment                  ; Value ; From ; To                                                                   ;
+-----------------------------+-------+------+----------------------------------------------------------------------+
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[7]                                  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[6]                                  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[5]                                  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[4]                                  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[3]                                  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[2]                                  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[1]                                  ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[0]                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; select_n_to_the_cfi_flash_0                                          ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[21]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[20]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[19]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[18]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[17]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[16]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[15]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[14]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[13]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[12]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[11]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[10]                                       ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[9]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[8]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[7]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[6]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[5]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[4]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[3]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[2]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[1]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[0]                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_readn                                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; write_n_to_the_cfi_flash_0                                           ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[7]~reg0                             ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[6]~reg0                             ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[5]~reg0                             ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[4]~reg0                             ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[3]~reg0                             ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[2]~reg0                             ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[1]~reg0                             ;
; FAST_INPUT_REGISTER         ; ON    ; -    ; incoming_tri_state_bridge_0_data[0]~reg0                             ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[7]                               ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[6]                               ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[5]                               ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[4]                               ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[3]                               ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[2]                               ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[1]                               ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; d1_outgoing_tri_state_bridge_0_data[0]                               ;
; FAST_OUTPUT_ENABLE_REGISTER ; ON    ; -    ; d1_in_a_write_cycle                                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[21]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[20]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[19]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[18]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[17]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[16]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[15]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[14]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[13]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[12]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[11]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[10]~reg0                                  ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[9]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[8]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[7]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[6]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[5]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[4]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[3]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[2]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[1]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_address[0]~reg0                                   ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; select_n_to_the_cfi_flash_0~reg0                                     ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; tri_state_bridge_0_readn~reg0                                        ;
; FAST_OUTPUT_REGISTER        ; ON    ; -    ; write_n_to_the_cfi_flash_0~reg0                                      ;
+-----------------------------+-------+------+----------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch ;
+-------------------+-------+------+------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                     ;
+-------------------+-------+------+------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                               ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                          ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                             ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                             ;
+-------------------+-------+------+------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Source assignments for system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch ;
+-------------------+-------+------+------------------------------------------------------------------------------+
; Assignment        ; Value ; From ; To                                                                           ;
+-------------------+-------+------+------------------------------------------------------------------------------+
; PRESERVE_REGISTER ; ON    ; -    ; data_out                                                                     ;
; PRESERVE_REGISTER ; ON    ; -    ; data_out~reg0                                                                ;
; MAX_DELAY         ; 100ns ; -    ; data_in_d1                                                                   ;
; PRESERVE_REGISTER ; ON    ; -    ; data_in_d1                                                                   ;
+-------------------+-------+------+------------------------------------------------------------------------------+


+----------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst              ;
+------------------------------+-------+------+------------+
; Assignment                   ; Value ; From ; To         ;
+------------------------------+-------+------+------------+
; IGNORE_LCELL_BUFFERS         ; OFF   ; -    ; -          ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF   ; -    ; -          ;
; NOT_GATE_PUSH_BACK           ; OFF   ; -    ; CLR_SIGNAL ;
; POWER_UP_LEVEL               ; LOW   ; -    ; CLR_SIGNAL ;
+------------------------------+-------+------+------------+


+---------------------------------------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine ;
+----------------+-------+------+-------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                    ;
+----------------+-------+------+-------------------------------------------------------+
; POWER_UP_LEVEL ; Low   ; -    ; state[0]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[1]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[2]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[3]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[4]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[5]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[6]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[7]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[8]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[9]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[10]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[11]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[12]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[13]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[14]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[15]                                             ;
+----------------+-------+------+-------------------------------------------------------+


+---------------------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ;
+----------------------+-------+------+-------------------------------+
; Assignment           ; Value ; From ; To                            ;
+----------------------+-------+------+-------------------------------+
; AUTO_ROM_RECOGNITION ; OFF   ; -    ; -                             ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[0]               ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[1]               ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[2]               ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[3]               ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[4]               ;
+----------------------+-------+------+-------------------------------+


+----------------------------------------------------------------------------------------------+
; Source assignments for I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_mj01:auto_generated ;
+---------------------------------+--------------------+------+--------------------------------+
; Assignment                      ; Value              ; From ; To                             ;
+---------------------------------+--------------------+------+--------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                              ;
+---------------------------------+--------------------+------+--------------------------------+


+-------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: SDRAM_PLL:PLL1|altpll:altpll_component ;
+-------------------------------+-------------+---------------------------------------+
; Parameter Name                ; Value       ; Type                                  ;
+-------------------------------+-------------+---------------------------------------+
; OPERATION_MODE                ; NORMAL      ; Untyped                               ;
; PLL_TYPE                      ; FAST        ; Untyped                               ;
; QUALIFY_CONF_DONE             ; OFF         ; Untyped                               ;
; COMPENSATE_CLOCK              ; CLK0        ; Untyped                               ;
; SCAN_CHAIN                    ; LONG        ; Untyped                               ;
; PRIMARY_CLOCK                 ; INCLK0      ; Untyped                               ;
; INCLK0_INPUT_FREQUENCY        ; 20000       ; Integer                               ;
; INCLK1_INPUT_FREQUENCY        ; 0           ; Untyped                               ;
; GATE_LOCK_SIGNAL              ; NO          ; Untyped                               ;
; GATE_LOCK_COUNTER             ; 0           ; Untyped                               ;
; LOCK_HIGH                     ; 1           ; Untyped                               ;
; LOCK_LOW                      ; 1           ; Untyped                               ;
; VALID_LOCK_MULTIPLIER         ; 1           ; Untyped                               ;
; INVALID_LOCK_MULTIPLIER       ; 5           ; Untyped                               ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF         ; Untyped                               ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF         ; Untyped                               ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF         ; Untyped                               ;
; SKIP_VCO                      ; OFF         ; Untyped                               ;
; SWITCH_OVER_COUNTER           ; 0           ; Untyped                               ;
; SWITCH_OVER_TYPE              ; AUTO        ; Untyped                               ;
; FEEDBACK_SOURCE               ; EXTCLK0     ; Untyped                               ;
; BANDWIDTH                     ; 0           ; Untyped                               ;
; BANDWIDTH_TYPE                ; AUTO        ; Untyped                               ;
; SPREAD_FREQUENCY              ; 0           ; Untyped                               ;
; DOWN_SPREAD                   ; 0           ; Untyped                               ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF         ; Untyped                               ;
; CLK5_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK4_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK3_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK2_MULTIPLY_BY              ; 1           ; Integer                               ;
; CLK1_MULTIPLY_BY              ; 2           ; Integer                               ;
; CLK0_MULTIPLY_BY              ; 1           ; Integer                               ;
; CLK5_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK4_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK3_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK2_DIVIDE_BY                ; 2           ; Integer                               ;
; CLK1_DIVIDE_BY                ; 1           ; Integer                               ;
; CLK0_DIVIDE_BY                ; 1           ; Integer                               ;
; CLK5_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK4_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK3_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK2_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK1_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK0_PHASE_SHIFT              ; -3000       ; Untyped                               ;
; CLK5_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK4_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK3_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK2_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK1_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK0_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK5_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK4_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK3_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK2_DUTY_CYCLE               ; 50          ; Integer                               ;
; CLK1_DUTY_CYCLE               ; 50          ; Integer                               ;
; CLK0_DUTY_CYCLE               ; 50          ; Integer                               ;
; EXTCLK3_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK2_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK1_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK0_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK3_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK2_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK1_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK0_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK3_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK2_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK1_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK0_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK3_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK2_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK1_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK0_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK3_DUTY_CYCLE            ; 50          ; Untyped                               ;
; EXTCLK2_DUTY_CYCLE            ; 50          ; Untyped                               ;
; EXTCLK1_DUTY_CYCLE            ; 50          ; Untyped                               ;
; EXTCLK0_DUTY_CYCLE            ; 50          ; Untyped                               ;
; VCO_MULTIPLY_BY               ; 0           ; Untyped                               ;
; VCO_DIVIDE_BY                 ; 0           ; Untyped                               ;
; SCLKOUT0_PHASE_SHIFT          ; 0           ; Untyped                               ;
; SCLKOUT1_PHASE_SHIFT          ; 0           ; Untyped                               ;
; VCO_MIN                       ; 0           ; Untyped                               ;
; VCO_MAX                       ; 0           ; Untyped                               ;
; VCO_CENTER                    ; 0           ; Untyped                               ;
; PFD_MIN                       ; 0           ; Untyped                               ;
; PFD_MAX                       ; 0           ; Untyped                               ;
; M_INITIAL                     ; 0           ; Untyped                               ;
; M                             ; 0           ; Untyped                               ;
; N                             ; 1           ; Untyped                               ;
; M2                            ; 1           ; Untyped                               ;
; N2                            ; 1           ; Untyped                               ;
; SS                            ; 1           ; Untyped                               ;
; C0_HIGH                       ; 0           ; Untyped                               ;
; C1_HIGH                       ; 0           ; Untyped                               ;
; C2_HIGH                       ; 0           ; Untyped                               ;
; C3_HIGH                       ; 0           ; Untyped                               ;
; C4_HIGH                       ; 0           ; Untyped                               ;
; C5_HIGH                       ; 0           ; Untyped                               ;
; C0_LOW                        ; 0           ; Untyped                               ;
; C1_LOW                        ; 0           ; Untyped                               ;
; C2_LOW                        ; 0           ; Untyped                               ;
; C3_LOW                        ; 0           ; Untyped                               ;
; C4_LOW                        ; 0           ; Untyped                               ;
; C5_LOW                        ; 0           ; Untyped                               ;
; C0_INITIAL                    ; 0           ; Untyped                               ;
; C1_INITIAL                    ; 0           ; Untyped                               ;
; C2_INITIAL                    ; 0           ; Untyped                               ;
; C3_INITIAL                    ; 0           ; Untyped                               ;
; C4_INITIAL                    ; 0           ; Untyped                               ;
; C5_INITIAL                    ; 0           ; Untyped                               ;
; C0_MODE                       ; BYPASS      ; Untyped                               ;
; C1_MODE                       ; BYPASS      ; Untyped                               ;
; C2_MODE                       ; BYPASS      ; Untyped                               ;
; C3_MODE                       ; BYPASS      ; Untyped                               ;
; C4_MODE                       ; BYPASS      ; Untyped                               ;
; C5_MODE                       ; BYPASS      ; Untyped                               ;
; C0_PH                         ; 0           ; Untyped                               ;
; C1_PH                         ; 0           ; Untyped                               ;
; C2_PH                         ; 0           ; Untyped                               ;
; C3_PH                         ; 0           ; Untyped                               ;
; C4_PH                         ; 0           ; Untyped                               ;
; C5_PH                         ; 0           ; Untyped                               ;
; L0_HIGH                       ; 1           ; Untyped                               ;
; L1_HIGH                       ; 1           ; Untyped                               ;
; G0_HIGH                       ; 1           ; Untyped                               ;
; G1_HIGH                       ; 1           ; Untyped                               ;
; G2_HIGH                       ; 1           ; Untyped                               ;
; G3_HIGH                       ; 1           ; Untyped                               ;
; E0_HIGH                       ; 1           ; Untyped                               ;
; E1_HIGH                       ; 1           ; Untyped                               ;
; E2_HIGH                       ; 1           ; Untyped                               ;
; E3_HIGH                       ; 1           ; Untyped                               ;
; L0_LOW                        ; 1           ; Untyped                               ;
; L1_LOW                        ; 1           ; Untyped                               ;
; G0_LOW                        ; 1           ; Untyped                               ;
; G1_LOW                        ; 1           ; Untyped                               ;
; G2_LOW                        ; 1           ; Untyped                               ;
; G3_LOW                        ; 1           ; Untyped                               ;
; E0_LOW                        ; 1           ; Untyped                               ;
; E1_LOW                        ; 1           ; Untyped                               ;
; E2_LOW                        ; 1           ; Untyped                               ;
; E3_LOW                        ; 1           ; Untyped                               ;
; L0_INITIAL                    ; 1           ; Untyped                               ;
; L1_INITIAL                    ; 1           ; Untyped                               ;
; G0_INITIAL                    ; 1           ; Untyped                               ;
; G1_INITIAL                    ; 1           ; Untyped                               ;
; G2_INITIAL                    ; 1           ; Untyped                               ;
; G3_INITIAL                    ; 1           ; Untyped                               ;
; E0_INITIAL                    ; 1           ; Untyped                               ;
; E1_INITIAL                    ; 1           ; Untyped                               ;
; E2_INITIAL                    ; 1           ; Untyped                               ;
; E3_INITIAL                    ; 1           ; Untyped                               ;
; L0_MODE                       ; BYPASS      ; Untyped                               ;
; L1_MODE                       ; BYPASS      ; Untyped                               ;
; G0_MODE                       ; BYPASS      ; Untyped                               ;
; G1_MODE                       ; BYPASS      ; Untyped                               ;
; G2_MODE                       ; BYPASS      ; Untyped                               ;
; G3_MODE                       ; BYPASS      ; Untyped                               ;
; E0_MODE                       ; BYPASS      ; Untyped                               ;
; E1_MODE                       ; BYPASS      ; Untyped                               ;
; E2_MODE                       ; BYPASS      ; Untyped                               ;
; E3_MODE                       ; BYPASS      ; Untyped                               ;
; L0_PH                         ; 0           ; Untyped                               ;
; L1_PH                         ; 0           ; Untyped                               ;
; G0_PH                         ; 0           ; Untyped                               ;
; G1_PH                         ; 0           ; Untyped                               ;
; G2_PH                         ; 0           ; Untyped                               ;
; G3_PH                         ; 0           ; Untyped                               ;
; E0_PH                         ; 0           ; Untyped                               ;
; E1_PH                         ; 0           ; Untyped                               ;
; E2_PH                         ; 0           ; Untyped                               ;
; E3_PH                         ; 0           ; Untyped                               ;
; M_PH                          ; 0           ; Untyped                               ;
; C1_USE_CASC_IN                ; 0           ; Untyped                               ;
; C2_USE_CASC_IN                ; 0           ; Untyped                               ;
; C3_USE_CASC_IN                ; 0           ; Untyped                               ;
; C4_USE_CASC_IN                ; 0           ; Untyped                               ;
; C5_USE_CASC_IN                ; 0           ; Untyped                               ;
; CLK0_COUNTER                  ; G0          ; Untyped                               ;
; CLK1_COUNTER                  ; G0          ; Untyped                               ;
; CLK2_COUNTER                  ; G0          ; Untyped                               ;
; CLK3_COUNTER                  ; G0          ; Untyped                               ;
; CLK4_COUNTER                  ; G0          ; Untyped                               ;
; CLK5_COUNTER                  ; G0          ; Untyped                               ;
; L0_TIME_DELAY                 ; 0           ; Untyped                               ;
; L1_TIME_DELAY                 ; 0           ; Untyped                               ;
; G0_TIME_DELAY                 ; 0           ; Untyped                               ;
; G1_TIME_DELAY                 ; 0           ; Untyped                               ;
; G2_TIME_DELAY                 ; 0           ; Untyped                               ;
; G3_TIME_DELAY                 ; 0           ; Untyped                               ;
; E0_TIME_DELAY                 ; 0           ; Untyped                               ;
; E1_TIME_DELAY                 ; 0           ; Untyped                               ;
; E2_TIME_DELAY                 ; 0           ; Untyped                               ;
; E3_TIME_DELAY                 ; 0           ; Untyped                               ;
; M_TIME_DELAY                  ; 0           ; Untyped                               ;
; N_TIME_DELAY                  ; 0           ; Untyped                               ;
; EXTCLK3_COUNTER               ; E3          ; Untyped                               ;
; EXTCLK2_COUNTER               ; E2          ; Untyped                               ;
; EXTCLK1_COUNTER               ; E1          ; Untyped                               ;
; EXTCLK0_COUNTER               ; E0          ; Untyped                               ;
; ENABLE0_COUNTER               ; L0          ; Untyped                               ;
; ENABLE1_COUNTER               ; L0          ; Untyped                               ;
; CHARGE_PUMP_CURRENT           ; 2           ; Untyped                               ;
; LOOP_FILTER_R                 ;  1.000000   ; Untyped                               ;
; LOOP_FILTER_C                 ; 5           ; Untyped                               ;
; VCO_POST_SCALE                ; 0           ; Untyped                               ;
; CLK2_OUTPUT_FREQUENCY         ; 0           ; Untyped                               ;
; CLK1_OUTPUT_FREQUENCY         ; 0           ; Untyped                               ;
; CLK0_OUTPUT_FREQUENCY         ; 0           ; Untyped                               ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II  ; Untyped                               ;
; PORT_CLKENA0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA2                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA3                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA4                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA5                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA0               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA1               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA2               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA3               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK2                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK3                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKBAD0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKBAD1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK0                     ; PORT_USED   ; Untyped                               ;
; PORT_CLK1                     ; PORT_USED   ; Untyped                               ;
; PORT_CLK2                     ; PORT_USED   ; Untyped                               ;
; PORT_CLK3                     ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK4                     ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK5                     ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANDATA                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANDATAOUT              ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANDONE                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCLKOUT1                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCLKOUT0                 ; PORT_UNUSED ; Untyped                               ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKLOSS                  ; PORT_UNUSED ; Untyped                               ;
; PORT_INCLK1                   ; PORT_UNUSED ; Untyped                               ;
; PORT_INCLK0                   ; PORT_USED   ; Untyped                               ;
; PORT_FBIN                     ; PORT_UNUSED ; Untyped                               ;
; PORT_PLLENA                   ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKSWITCH                ; PORT_UNUSED ; Untyped                               ;
; PORT_ARESET                   ; PORT_UNUSED ; Untyped                               ;
; PORT_PFDENA                   ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANCLK                  ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANACLR                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANREAD                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANWRITE                ; PORT_UNUSED ; Untyped                               ;
; PORT_ENABLE0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_ENABLE1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_LOCKED                   ; PORT_UNUSED ; Untyped                               ;
; M_TEST_SOURCE                 ; 5           ; Untyped                               ;
; C0_TEST_SOURCE                ; 5           ; Untyped                               ;
; C1_TEST_SOURCE                ; 5           ; Untyped                               ;
; C2_TEST_SOURCE                ; 5           ; Untyped                               ;
; C3_TEST_SOURCE                ; 5           ; Untyped                               ;
; C4_TEST_SOURCE                ; 5           ; Untyped                               ;
; C5_TEST_SOURCE                ; 5           ; Untyped                               ;
; DEVICE_FAMILY                 ; Cyclone II  ; Untyped                               ;
; AUTO_CARRY_CHAINS             ; ON          ; AUTO_CARRY                            ;
; IGNORE_CARRY_BUFFERS          ; OFF         ; IGNORE_CARRY                          ;
; AUTO_CASCADE_CHAINS           ; ON          ; AUTO_CASCADE                          ;
; IGNORE_CASCADE_BUFFERS        ; OFF         ; IGNORE_CASCADE                        ;
+-------------------------------+-------------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Audio_PLL:PLL2|altpll:altpll_component ;
+-------------------------------+-------------+---------------------------------------+
; Parameter Name                ; Value       ; Type                                  ;
+-------------------------------+-------------+---------------------------------------+
; OPERATION_MODE                ; NORMAL      ; Untyped                               ;
; PLL_TYPE                      ; FAST        ; Untyped                               ;
; QUALIFY_CONF_DONE             ; OFF         ; Untyped                               ;
; COMPENSATE_CLOCK              ; CLK0        ; Untyped                               ;
; SCAN_CHAIN                    ; LONG        ; Untyped                               ;
; PRIMARY_CLOCK                 ; INCLK0      ; Untyped                               ;
; INCLK0_INPUT_FREQUENCY        ; 37037       ; Integer                               ;
; INCLK1_INPUT_FREQUENCY        ; 0           ; Untyped                               ;
; GATE_LOCK_SIGNAL              ; NO          ; Untyped                               ;
; GATE_LOCK_COUNTER             ; 0           ; Untyped                               ;
; LOCK_HIGH                     ; 1           ; Untyped                               ;
; LOCK_LOW                      ; 1           ; Untyped                               ;
; VALID_LOCK_MULTIPLIER         ; 1           ; Untyped                               ;
; INVALID_LOCK_MULTIPLIER       ; 5           ; Untyped                               ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF         ; Untyped                               ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF         ; Untyped                               ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF         ; Untyped                               ;
; SKIP_VCO                      ; OFF         ; Untyped                               ;
; SWITCH_OVER_COUNTER           ; 0           ; Untyped                               ;
; SWITCH_OVER_TYPE              ; AUTO        ; Untyped                               ;
; FEEDBACK_SOURCE               ; EXTCLK0     ; Untyped                               ;
; BANDWIDTH                     ; 0           ; Untyped                               ;
; BANDWIDTH_TYPE                ; AUTO        ; Untyped                               ;
; SPREAD_FREQUENCY              ; 0           ; Untyped                               ;
; DOWN_SPREAD                   ; 0           ; Untyped                               ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF         ; Untyped                               ;
; CLK5_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK4_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK3_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK2_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK1_MULTIPLY_BY              ; 1           ; Untyped                               ;
; CLK0_MULTIPLY_BY              ; 92          ; Integer                               ;
; CLK5_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK4_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK3_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK2_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK1_DIVIDE_BY                ; 1           ; Untyped                               ;
; CLK0_DIVIDE_BY                ; 135         ; Integer                               ;
; CLK5_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK4_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK3_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK2_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK1_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK0_PHASE_SHIFT              ; 0           ; Untyped                               ;
; CLK5_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK4_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK3_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK2_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK1_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK0_TIME_DELAY               ; 0           ; Untyped                               ;
; CLK5_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK4_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK3_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK2_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK1_DUTY_CYCLE               ; 50          ; Untyped                               ;
; CLK0_DUTY_CYCLE               ; 50          ; Integer                               ;
; EXTCLK3_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK2_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK1_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK0_MULTIPLY_BY           ; 1           ; Untyped                               ;
; EXTCLK3_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK2_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK1_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK0_DIVIDE_BY             ; 1           ; Untyped                               ;
; EXTCLK3_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK2_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK1_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK0_PHASE_SHIFT           ; 0           ; Untyped                               ;
; EXTCLK3_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK2_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK1_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK0_TIME_DELAY            ; 0           ; Untyped                               ;
; EXTCLK3_DUTY_CYCLE            ; 50          ; Untyped                               ;
; EXTCLK2_DUTY_CYCLE            ; 50          ; Untyped                               ;
; EXTCLK1_DUTY_CYCLE            ; 50          ; Untyped                               ;
; EXTCLK0_DUTY_CYCLE            ; 50          ; Untyped                               ;
; VCO_MULTIPLY_BY               ; 0           ; Untyped                               ;
; VCO_DIVIDE_BY                 ; 0           ; Untyped                               ;
; SCLKOUT0_PHASE_SHIFT          ; 0           ; Untyped                               ;
; SCLKOUT1_PHASE_SHIFT          ; 0           ; Untyped                               ;
; VCO_MIN                       ; 0           ; Untyped                               ;
; VCO_MAX                       ; 0           ; Untyped                               ;
; VCO_CENTER                    ; 0           ; Untyped                               ;
; PFD_MIN                       ; 0           ; Untyped                               ;
; PFD_MAX                       ; 0           ; Untyped                               ;
; M_INITIAL                     ; 0           ; Untyped                               ;
; M                             ; 0           ; Untyped                               ;
; N                             ; 1           ; Untyped                               ;
; M2                            ; 1           ; Untyped                               ;
; N2                            ; 1           ; Untyped                               ;
; SS                            ; 1           ; Untyped                               ;
; C0_HIGH                       ; 0           ; Untyped                               ;
; C1_HIGH                       ; 0           ; Untyped                               ;
; C2_HIGH                       ; 0           ; Untyped                               ;
; C3_HIGH                       ; 0           ; Untyped                               ;
; C4_HIGH                       ; 0           ; Untyped                               ;
; C5_HIGH                       ; 0           ; Untyped                               ;
; C0_LOW                        ; 0           ; Untyped                               ;
; C1_LOW                        ; 0           ; Untyped                               ;
; C2_LOW                        ; 0           ; Untyped                               ;
; C3_LOW                        ; 0           ; Untyped                               ;
; C4_LOW                        ; 0           ; Untyped                               ;
; C5_LOW                        ; 0           ; Untyped                               ;
; C0_INITIAL                    ; 0           ; Untyped                               ;
; C1_INITIAL                    ; 0           ; Untyped                               ;
; C2_INITIAL                    ; 0           ; Untyped                               ;
; C3_INITIAL                    ; 0           ; Untyped                               ;
; C4_INITIAL                    ; 0           ; Untyped                               ;
; C5_INITIAL                    ; 0           ; Untyped                               ;
; C0_MODE                       ; BYPASS      ; Untyped                               ;
; C1_MODE                       ; BYPASS      ; Untyped                               ;
; C2_MODE                       ; BYPASS      ; Untyped                               ;
; C3_MODE                       ; BYPASS      ; Untyped                               ;
; C4_MODE                       ; BYPASS      ; Untyped                               ;
; C5_MODE                       ; BYPASS      ; Untyped                               ;
; C0_PH                         ; 0           ; Untyped                               ;
; C1_PH                         ; 0           ; Untyped                               ;
; C2_PH                         ; 0           ; Untyped                               ;
; C3_PH                         ; 0           ; Untyped                               ;
; C4_PH                         ; 0           ; Untyped                               ;
; C5_PH                         ; 0           ; Untyped                               ;
; L0_HIGH                       ; 1           ; Untyped                               ;
; L1_HIGH                       ; 1           ; Untyped                               ;
; G0_HIGH                       ; 1           ; Untyped                               ;
; G1_HIGH                       ; 1           ; Untyped                               ;
; G2_HIGH                       ; 1           ; Untyped                               ;
; G3_HIGH                       ; 1           ; Untyped                               ;
; E0_HIGH                       ; 1           ; Untyped                               ;
; E1_HIGH                       ; 1           ; Untyped                               ;
; E2_HIGH                       ; 1           ; Untyped                               ;
; E3_HIGH                       ; 1           ; Untyped                               ;
; L0_LOW                        ; 1           ; Untyped                               ;
; L1_LOW                        ; 1           ; Untyped                               ;
; G0_LOW                        ; 1           ; Untyped                               ;
; G1_LOW                        ; 1           ; Untyped                               ;
; G2_LOW                        ; 1           ; Untyped                               ;
; G3_LOW                        ; 1           ; Untyped                               ;
; E0_LOW                        ; 1           ; Untyped                               ;
; E1_LOW                        ; 1           ; Untyped                               ;
; E2_LOW                        ; 1           ; Untyped                               ;
; E3_LOW                        ; 1           ; Untyped                               ;
; L0_INITIAL                    ; 1           ; Untyped                               ;
; L1_INITIAL                    ; 1           ; Untyped                               ;
; G0_INITIAL                    ; 1           ; Untyped                               ;
; G1_INITIAL                    ; 1           ; Untyped                               ;
; G2_INITIAL                    ; 1           ; Untyped                               ;
; G3_INITIAL                    ; 1           ; Untyped                               ;
; E0_INITIAL                    ; 1           ; Untyped                               ;
; E1_INITIAL                    ; 1           ; Untyped                               ;
; E2_INITIAL                    ; 1           ; Untyped                               ;
; E3_INITIAL                    ; 1           ; Untyped                               ;
; L0_MODE                       ; BYPASS      ; Untyped                               ;
; L1_MODE                       ; BYPASS      ; Untyped                               ;
; G0_MODE                       ; BYPASS      ; Untyped                               ;
; G1_MODE                       ; BYPASS      ; Untyped                               ;
; G2_MODE                       ; BYPASS      ; Untyped                               ;
; G3_MODE                       ; BYPASS      ; Untyped                               ;
; E0_MODE                       ; BYPASS      ; Untyped                               ;
; E1_MODE                       ; BYPASS      ; Untyped                               ;
; E2_MODE                       ; BYPASS      ; Untyped                               ;
; E3_MODE                       ; BYPASS      ; Untyped                               ;
; L0_PH                         ; 0           ; Untyped                               ;
; L1_PH                         ; 0           ; Untyped                               ;
; G0_PH                         ; 0           ; Untyped                               ;
; G1_PH                         ; 0           ; Untyped                               ;
; G2_PH                         ; 0           ; Untyped                               ;
; G3_PH                         ; 0           ; Untyped                               ;
; E0_PH                         ; 0           ; Untyped                               ;
; E1_PH                         ; 0           ; Untyped                               ;
; E2_PH                         ; 0           ; Untyped                               ;
; E3_PH                         ; 0           ; Untyped                               ;
; M_PH                          ; 0           ; Untyped                               ;
; C1_USE_CASC_IN                ; 0           ; Untyped                               ;
; C2_USE_CASC_IN                ; 0           ; Untyped                               ;
; C3_USE_CASC_IN                ; 0           ; Untyped                               ;
; C4_USE_CASC_IN                ; 0           ; Untyped                               ;
; C5_USE_CASC_IN                ; 0           ; Untyped                               ;
; CLK0_COUNTER                  ; G0          ; Untyped                               ;
; CLK1_COUNTER                  ; G0          ; Untyped                               ;
; CLK2_COUNTER                  ; G0          ; Untyped                               ;
; CLK3_COUNTER                  ; G0          ; Untyped                               ;
; CLK4_COUNTER                  ; G0          ; Untyped                               ;
; CLK5_COUNTER                  ; G0          ; Untyped                               ;
; L0_TIME_DELAY                 ; 0           ; Untyped                               ;
; L1_TIME_DELAY                 ; 0           ; Untyped                               ;
; G0_TIME_DELAY                 ; 0           ; Untyped                               ;
; G1_TIME_DELAY                 ; 0           ; Untyped                               ;
; G2_TIME_DELAY                 ; 0           ; Untyped                               ;
; G3_TIME_DELAY                 ; 0           ; Untyped                               ;
; E0_TIME_DELAY                 ; 0           ; Untyped                               ;
; E1_TIME_DELAY                 ; 0           ; Untyped                               ;
; E2_TIME_DELAY                 ; 0           ; Untyped                               ;
; E3_TIME_DELAY                 ; 0           ; Untyped                               ;
; M_TIME_DELAY                  ; 0           ; Untyped                               ;
; N_TIME_DELAY                  ; 0           ; Untyped                               ;
; EXTCLK3_COUNTER               ; E3          ; Untyped                               ;
; EXTCLK2_COUNTER               ; E2          ; Untyped                               ;
; EXTCLK1_COUNTER               ; E1          ; Untyped                               ;
; EXTCLK0_COUNTER               ; E0          ; Untyped                               ;
; ENABLE0_COUNTER               ; L0          ; Untyped                               ;
; ENABLE1_COUNTER               ; L0          ; Untyped                               ;
; CHARGE_PUMP_CURRENT           ; 2           ; Untyped                               ;
; LOOP_FILTER_R                 ;  1.000000   ; Untyped                               ;
; LOOP_FILTER_C                 ; 5           ; Untyped                               ;
; VCO_POST_SCALE                ; 0           ; Untyped                               ;
; CLK2_OUTPUT_FREQUENCY         ; 0           ; Untyped                               ;
; CLK1_OUTPUT_FREQUENCY         ; 0           ; Untyped                               ;
; CLK0_OUTPUT_FREQUENCY         ; 0           ; Untyped                               ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II  ; Untyped                               ;
; PORT_CLKENA0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA2                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA3                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA4                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKENA5                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA0               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA1               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA2               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLKENA3               ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK2                  ; PORT_UNUSED ; Untyped                               ;
; PORT_EXTCLK3                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKBAD0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKBAD1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK0                     ; PORT_USED   ; Untyped                               ;
; PORT_CLK1                     ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK2                     ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK3                     ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK4                     ; PORT_UNUSED ; Untyped                               ;
; PORT_CLK5                     ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANDATA                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANDATAOUT              ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANDONE                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCLKOUT1                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCLKOUT0                 ; PORT_UNUSED ; Untyped                               ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKLOSS                  ; PORT_UNUSED ; Untyped                               ;
; PORT_INCLK1                   ; PORT_UNUSED ; Untyped                               ;
; PORT_INCLK0                   ; PORT_USED   ; Untyped                               ;
; PORT_FBIN                     ; PORT_UNUSED ; Untyped                               ;
; PORT_PLLENA                   ; PORT_UNUSED ; Untyped                               ;
; PORT_CLKSWITCH                ; PORT_UNUSED ; Untyped                               ;
; PORT_ARESET                   ; PORT_USED   ; Untyped                               ;
; PORT_PFDENA                   ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANCLK                  ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANACLR                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANREAD                 ; PORT_UNUSED ; Untyped                               ;
; PORT_SCANWRITE                ; PORT_UNUSED ; Untyped                               ;
; PORT_ENABLE0                  ; PORT_UNUSED ; Untyped                               ;
; PORT_ENABLE1                  ; PORT_UNUSED ; Untyped                               ;
; PORT_LOCKED                   ; PORT_UNUSED ; Untyped                               ;
; M_TEST_SOURCE                 ; 5           ; Untyped                               ;
; C0_TEST_SOURCE                ; 5           ; Untyped                               ;
; C1_TEST_SOURCE                ; 5           ; Untyped                               ;
; C2_TEST_SOURCE                ; 5           ; Untyped                               ;
; C3_TEST_SOURCE                ; 5           ; Untyped                               ;
; C4_TEST_SOURCE                ; 5           ; Untyped                               ;
; C5_TEST_SOURCE                ; 5           ; Untyped                               ;
; DEVICE_FAMILY                 ; Cyclone II  ; Untyped                               ;
; AUTO_CARRY_CHAINS             ; ON          ; AUTO_CARRY                            ;
; IGNORE_CARRY_BUFFERS          ; OFF         ; IGNORE_CARRY                          ;
; AUTO_CASCADE_CHAINS           ; ON          ; AUTO_CASCADE                          ;
; IGNORE_CASCADE_BUFFERS        ; OFF         ; IGNORE_CASCADE                        ;
+-------------------------------+-------------+---------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data ;
+----------------+--------+-----------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                              ;
+----------------+--------+-----------------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                            ;
+----------------+--------+-----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------+
; Parameter Name                     ; Value           ; Type                                                                           ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                                        ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                                     ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                                   ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                                   ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                                 ;
; OPERATION_MODE                     ; DUAL_PORT       ; Untyped                                                                        ;
; WIDTH_A                            ; 32              ; Integer                                                                        ;
; WIDTHAD_A                          ; 10              ; Integer                                                                        ;
; NUMWORDS_A                         ; 1024            ; Integer                                                                        ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                                                                        ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                                        ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                                        ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                                        ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                                                        ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                                        ;
; WIDTH_B                            ; 32              ; Integer                                                                        ;
; WIDTHAD_B                          ; 10              ; Integer                                                                        ;
; NUMWORDS_B                         ; 1024            ; Integer                                                                        ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                                        ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                                        ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                                        ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                                        ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                                                                        ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                                        ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                                                        ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                        ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                                        ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                                        ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                        ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                                        ;
; WIDTH_BYTEENA_A                    ; 1               ; Untyped                                                                        ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                                                                        ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                                        ;
; BYTE_SIZE                          ; 8               ; Untyped                                                                        ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE       ; Untyped                                                                        ;
; INIT_FILE                          ; UNUSED          ; Untyped                                                                        ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                                        ;
; MAXIMUM_DEPTH                      ; 0               ; Integer                                                                        ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                                                                        ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                                                        ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                                                        ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                                                        ;
; DEVICE_FAMILY                      ; Cyclone II      ; Untyped                                                                        ;
; CBXI_PARAMETER                     ; altsyncram_cub1 ; Untyped                                                                        ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag ;
+----------------+----------------------+-------------------------------------------------------------------+
; Parameter Name ; Value                ; Type                                                              ;
+----------------+----------------------+-------------------------------------------------------------------+
; lpm_file       ; cpu_0_ic_tag_ram.mif ; String                                                            ;
+----------------+----------------------+-------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+-------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                    ;
+------------------------------------+----------------------+-------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                 ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                              ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                            ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                            ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                          ;
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                                                                 ;
; WIDTH_A                            ; 20                   ; Integer                                                                 ;
; WIDTHAD_A                          ; 7                    ; Integer                                                                 ;
; NUMWORDS_A                         ; 128                  ; Integer                                                                 ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                 ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                 ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                 ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                 ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                 ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                 ;
; WIDTH_B                            ; 20                   ; Integer                                                                 ;
; WIDTHAD_B                          ; 7                    ; Integer                                                                 ;
; NUMWORDS_B                         ; 128                  ; Integer                                                                 ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                 ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                 ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                 ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                                                                 ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                 ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                 ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                 ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                 ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                 ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                 ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                 ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                 ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                 ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                 ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                 ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                 ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                 ;
; INIT_FILE                          ; cpu_0_ic_tag_ram.mif ; Untyped                                                                 ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                 ;
; MAXIMUM_DEPTH                      ; 0                    ; Integer                                                                 ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                 ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                 ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                 ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                 ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                                                 ;
; CBXI_PARAMETER                     ; altsyncram_tke1      ; Untyped                                                                 ;
+------------------------------------+----------------------+-------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht ;
+----------------+-------------------+----------------------------------------------------------------+
; Parameter Name ; Value             ; Type                                                           ;
+----------------+-------------------+----------------------------------------------------------------+
; lpm_file       ; cpu_0_bht_ram.mif ; String                                                         ;
+----------------+-------------------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram ;
+------------------------------------+-------------------+----------------------------------------------------------------------+
; Parameter Name                     ; Value             ; Type                                                                 ;
+------------------------------------+-------------------+----------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                 ; Untyped                                                              ;
; AUTO_CARRY_CHAINS                  ; ON                ; AUTO_CARRY                                                           ;
; IGNORE_CARRY_BUFFERS               ; OFF               ; IGNORE_CARRY                                                         ;
; AUTO_CASCADE_CHAINS                ; ON                ; AUTO_CASCADE                                                         ;
; IGNORE_CASCADE_BUFFERS             ; OFF               ; IGNORE_CASCADE                                                       ;
; OPERATION_MODE                     ; DUAL_PORT         ; Untyped                                                              ;
; WIDTH_A                            ; 2                 ; Integer                                                              ;
; WIDTHAD_A                          ; 8                 ; Integer                                                              ;
; NUMWORDS_A                         ; 256               ; Integer                                                              ;
; OUTDATA_REG_A                      ; UNREGISTERED      ; Untyped                                                              ;
; ADDRESS_ACLR_A                     ; NONE              ; Untyped                                                              ;
; OUTDATA_ACLR_A                     ; NONE              ; Untyped                                                              ;
; WRCONTROL_ACLR_A                   ; NONE              ; Untyped                                                              ;
; INDATA_ACLR_A                      ; NONE              ; Untyped                                                              ;
; BYTEENA_ACLR_A                     ; NONE              ; Untyped                                                              ;
; WIDTH_B                            ; 2                 ; Integer                                                              ;
; WIDTHAD_B                          ; 8                 ; Integer                                                              ;
; NUMWORDS_B                         ; 256               ; Integer                                                              ;
; INDATA_REG_B                       ; CLOCK1            ; Untyped                                                              ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1            ; Untyped                                                              ;
; RDCONTROL_REG_B                    ; CLOCK1            ; Untyped                                                              ;
; ADDRESS_REG_B                      ; CLOCK1            ; Untyped                                                              ;
; OUTDATA_REG_B                      ; UNREGISTERED      ; Untyped                                                              ;
; BYTEENA_REG_B                      ; CLOCK1            ; Untyped                                                              ;
; INDATA_ACLR_B                      ; NONE              ; Untyped                                                              ;
; WRCONTROL_ACLR_B                   ; NONE              ; Untyped                                                              ;
; ADDRESS_ACLR_B                     ; NONE              ; Untyped                                                              ;
; OUTDATA_ACLR_B                     ; NONE              ; Untyped                                                              ;
; RDCONTROL_ACLR_B                   ; NONE              ; Untyped                                                              ;
; BYTEENA_ACLR_B                     ; NONE              ; Untyped                                                              ;
; WIDTH_BYTEENA_A                    ; 1                 ; Untyped                                                              ;
; WIDTH_BYTEENA_B                    ; 1                 ; Untyped                                                              ;
; RAM_BLOCK_TYPE                     ; AUTO              ; Untyped                                                              ;
; BYTE_SIZE                          ; 8                 ; Untyped                                                              ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA          ; Untyped                                                              ;
; INIT_FILE                          ; cpu_0_bht_ram.mif ; Untyped                                                              ;
; INIT_FILE_LAYOUT                   ; PORT_A            ; Untyped                                                              ;
; MAXIMUM_DEPTH                      ; 0                 ; Integer                                                              ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL            ; Untyped                                                              ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL            ; Untyped                                                              ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL            ; Untyped                                                              ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL            ; Untyped                                                              ;
; DEVICE_FAMILY                      ; Cyclone II        ; Untyped                                                              ;
; CBXI_PARAMETER                     ; altsyncram_q8e1   ; Untyped                                                              ;
+------------------------------------+-------------------+----------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a ;
+----------------+--------------------+---------------------------------------------------------------------------------------+
; Parameter Name ; Value              ; Type                                                                                  ;
+----------------+--------------------+---------------------------------------------------------------------------------------+
; lpm_file       ; cpu_0_rf_ram_a.mif ; String                                                                                ;
+----------------+--------------------+---------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram ;
+------------------------------------+--------------------+---------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value              ; Type                                                                                        ;
+------------------------------------+--------------------+---------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                  ; Untyped                                                                                     ;
; AUTO_CARRY_CHAINS                  ; ON                 ; AUTO_CARRY                                                                                  ;
; IGNORE_CARRY_BUFFERS               ; OFF                ; IGNORE_CARRY                                                                                ;
; AUTO_CASCADE_CHAINS                ; ON                 ; AUTO_CASCADE                                                                                ;
; IGNORE_CASCADE_BUFFERS             ; OFF                ; IGNORE_CASCADE                                                                              ;
; OPERATION_MODE                     ; DUAL_PORT          ; Untyped                                                                                     ;
; WIDTH_A                            ; 32                 ; Integer                                                                                     ;
; WIDTHAD_A                          ; 5                  ; Integer                                                                                     ;
; NUMWORDS_A                         ; 32                 ; Integer                                                                                     ;
; OUTDATA_REG_A                      ; UNREGISTERED       ; Untyped                                                                                     ;
; ADDRESS_ACLR_A                     ; NONE               ; Untyped                                                                                     ;
; OUTDATA_ACLR_A                     ; NONE               ; Untyped                                                                                     ;
; WRCONTROL_ACLR_A                   ; NONE               ; Untyped                                                                                     ;
; INDATA_ACLR_A                      ; NONE               ; Untyped                                                                                     ;
; BYTEENA_ACLR_A                     ; NONE               ; Untyped                                                                                     ;
; WIDTH_B                            ; 32                 ; Integer                                                                                     ;
; WIDTHAD_B                          ; 5                  ; Integer                                                                                     ;
; NUMWORDS_B                         ; 32                 ; Integer                                                                                     ;
; INDATA_REG_B                       ; CLOCK1             ; Untyped                                                                                     ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1             ; Untyped                                                                                     ;
; RDCONTROL_REG_B                    ; CLOCK1             ; Untyped                                                                                     ;
; ADDRESS_REG_B                      ; CLOCK1             ; Untyped                                                                                     ;
; OUTDATA_REG_B                      ; UNREGISTERED       ; Untyped                                                                                     ;
; BYTEENA_REG_B                      ; CLOCK1             ; Untyped                                                                                     ;
; INDATA_ACLR_B                      ; NONE               ; Untyped                                                                                     ;
; WRCONTROL_ACLR_B                   ; NONE               ; Untyped                                                                                     ;
; ADDRESS_ACLR_B                     ; NONE               ; Untyped                                                                                     ;
; OUTDATA_ACLR_B                     ; NONE               ; Untyped                                                                                     ;
; RDCONTROL_ACLR_B                   ; NONE               ; Untyped                                                                                     ;
; BYTEENA_ACLR_B                     ; NONE               ; Untyped                                                                                     ;
; WIDTH_BYTEENA_A                    ; 1                  ; Untyped                                                                                     ;
; WIDTH_BYTEENA_B                    ; 1                  ; Untyped                                                                                     ;
; RAM_BLOCK_TYPE                     ; AUTO               ; Untyped                                                                                     ;
; BYTE_SIZE                          ; 8                  ; Untyped                                                                                     ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA           ; Untyped                                                                                     ;
; INIT_FILE                          ; cpu_0_rf_ram_a.mif ; Untyped                                                                                     ;
; INIT_FILE_LAYOUT                   ; PORT_A             ; Untyped                                                                                     ;
; MAXIMUM_DEPTH                      ; 0                  ; Integer                                                                                     ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL             ; Untyped                                                                                     ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL             ; Untyped                                                                                     ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL             ; Untyped                                                                                     ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL             ; Untyped                                                                                     ;
; DEVICE_FAMILY                      ; Cyclone II         ; Untyped                                                                                     ;
; CBXI_PARAMETER                     ; altsyncram_4be1    ; Untyped                                                                                     ;
+------------------------------------+--------------------+---------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b ;
+----------------+--------------------+---------------------------------------------------------------------------------------+
; Parameter Name ; Value              ; Type                                                                                  ;
+----------------+--------------------+---------------------------------------------------------------------------------------+
; lpm_file       ; cpu_0_rf_ram_b.mif ; String                                                                                ;
+----------------+--------------------+---------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram ;
+------------------------------------+--------------------+---------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value              ; Type                                                                                        ;
+------------------------------------+--------------------+---------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                  ; Untyped                                                                                     ;
; AUTO_CARRY_CHAINS                  ; ON                 ; AUTO_CARRY                                                                                  ;
; IGNORE_CARRY_BUFFERS               ; OFF                ; IGNORE_CARRY                                                                                ;
; AUTO_CASCADE_CHAINS                ; ON                 ; AUTO_CASCADE                                                                                ;
; IGNORE_CASCADE_BUFFERS             ; OFF                ; IGNORE_CASCADE                                                                              ;
; OPERATION_MODE                     ; DUAL_PORT          ; Untyped                                                                                     ;
; WIDTH_A                            ; 32                 ; Integer                                                                                     ;
; WIDTHAD_A                          ; 5                  ; Integer                                                                                     ;
; NUMWORDS_A                         ; 32                 ; Integer                                                                                     ;
; OUTDATA_REG_A                      ; UNREGISTERED       ; Untyped                                                                                     ;
; ADDRESS_ACLR_A                     ; NONE               ; Untyped                                                                                     ;
; OUTDATA_ACLR_A                     ; NONE               ; Untyped                                                                                     ;
; WRCONTROL_ACLR_A                   ; NONE               ; Untyped                                                                                     ;
; INDATA_ACLR_A                      ; NONE               ; Untyped                                                                                     ;
; BYTEENA_ACLR_A                     ; NONE               ; Untyped                                                                                     ;
; WIDTH_B                            ; 32                 ; Integer                                                                                     ;
; WIDTHAD_B                          ; 5                  ; Integer                                                                                     ;
; NUMWORDS_B                         ; 32                 ; Integer                                                                                     ;
; INDATA_REG_B                       ; CLOCK1             ; Untyped                                                                                     ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1             ; Untyped                                                                                     ;
; RDCONTROL_REG_B                    ; CLOCK1             ; Untyped                                                                                     ;
; ADDRESS_REG_B                      ; CLOCK1             ; Untyped                                                                                     ;
; OUTDATA_REG_B                      ; UNREGISTERED       ; Untyped                                                                                     ;
; BYTEENA_REG_B                      ; CLOCK1             ; Untyped                                                                                     ;
; INDATA_ACLR_B                      ; NONE               ; Untyped                                                                                     ;
; WRCONTROL_ACLR_B                   ; NONE               ; Untyped                                                                                     ;
; ADDRESS_ACLR_B                     ; NONE               ; Untyped                                                                                     ;
; OUTDATA_ACLR_B                     ; NONE               ; Untyped                                                                                     ;
; RDCONTROL_ACLR_B                   ; NONE               ; Untyped                                                                                     ;
; BYTEENA_ACLR_B                     ; NONE               ; Untyped                                                                                     ;
; WIDTH_BYTEENA_A                    ; 1                  ; Untyped                                                                                     ;
; WIDTH_BYTEENA_B                    ; 1                  ; Untyped                                                                                     ;
; RAM_BLOCK_TYPE                     ; AUTO               ; Untyped                                                                                     ;
; BYTE_SIZE                          ; 8                  ; Untyped                                                                                     ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA           ; Untyped                                                                                     ;
; INIT_FILE                          ; cpu_0_rf_ram_b.mif ; Untyped                                                                                     ;
; INIT_FILE_LAYOUT                   ; PORT_A             ; Untyped                                                                                     ;
; MAXIMUM_DEPTH                      ; 0                  ; Integer                                                                                     ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL             ; Untyped                                                                                     ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL             ; Untyped                                                                                     ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL             ; Untyped                                                                                     ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL             ; Untyped                                                                                     ;
; DEVICE_FAMILY                      ; Cyclone II         ; Untyped                                                                                     ;
; CBXI_PARAMETER                     ; altsyncram_5be1    ; Untyped                                                                                     ;
+------------------------------------+--------------------+---------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag ;
+----------------+----------------------+-------------------------------------------------------------------+
; Parameter Name ; Value                ; Type                                                              ;
+----------------+----------------------+-------------------------------------------------------------------+
; lpm_file       ; cpu_0_dc_tag_ram.mif ; String                                                            ;
+----------------+----------------------+-------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram ;
+------------------------------------+----------------------+-------------------------------------------------------------------------+
; Parameter Name                     ; Value                ; Type                                                                    ;
+------------------------------------+----------------------+-------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                                                                 ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                                                              ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                                                            ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                                                            ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                                                          ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT      ; Untyped                                                                 ;
; WIDTH_A                            ; 15                   ; Integer                                                                 ;
; WIDTHAD_A                          ; 9                    ; Integer                                                                 ;
; NUMWORDS_A                         ; 512                  ; Integer                                                                 ;
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                                                                 ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                                                                 ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                                                                 ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                                                                 ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                                                                 ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                                                                 ;
; WIDTH_B                            ; 15                   ; Integer                                                                 ;
; WIDTHAD_B                          ; 9                    ; Integer                                                                 ;
; NUMWORDS_B                         ; 512                  ; Integer                                                                 ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                                                                 ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                                                                 ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                                                                 ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                                                                 ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                                                                 ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                                                                 ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                                                                 ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                 ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                                                                 ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                                                                 ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                                                                 ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                                                                 ;
; WIDTH_BYTEENA_A                    ; 1                    ; Untyped                                                                 ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                                                                 ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                                                                 ;
; BYTE_SIZE                          ; 8                    ; Untyped                                                                 ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA             ; Untyped                                                                 ;
; INIT_FILE                          ; cpu_0_dc_tag_ram.mif ; Untyped                                                                 ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                                                                 ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                                                                 ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL               ; Untyped                                                                 ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                                                                 ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL               ; Untyped                                                                 ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                                                                 ;
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                                                                 ;
; CBXI_PARAMETER                     ; altsyncram_vf22      ; Untyped                                                                 ;
+------------------------------------+----------------------+-------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data ;
+----------------+--------+-----------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                              ;
+----------------+--------+-----------------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                            ;
+----------------+--------+-----------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------+
; Parameter Name                     ; Value           ; Type                                                                           ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                                        ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                                     ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                                   ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                                   ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                                 ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                                        ;
; WIDTH_A                            ; 32              ; Integer                                                                        ;
; WIDTHAD_A                          ; 9               ; Integer                                                                        ;
; NUMWORDS_A                         ; 512             ; Integer                                                                        ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                                                                        ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                                        ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                                        ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                                        ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                                                        ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                                        ;
; WIDTH_B                            ; 32              ; Integer                                                                        ;
; WIDTHAD_B                          ; 9               ; Integer                                                                        ;
; NUMWORDS_B                         ; 512             ; Integer                                                                        ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                                        ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                                        ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                                        ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                                        ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                                                                        ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                                        ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                                                        ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                        ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                                        ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                                        ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                        ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                                        ;
; WIDTH_BYTEENA_A                    ; 1               ; Untyped                                                                        ;
; WIDTH_BYTEENA_B                    ; 4               ; Integer                                                                        ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                                        ;
; BYTE_SIZE                          ; 8               ; Untyped                                                                        ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA        ; Untyped                                                                        ;
; INIT_FILE                          ; UNUSED          ; Untyped                                                                        ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                                        ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                                        ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                                                                        ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                                                        ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                                                        ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                                                        ;
; DEVICE_FAMILY                      ; Cyclone II      ; Untyped                                                                        ;
; CBXI_PARAMETER                     ; altsyncram_a422 ; Untyped                                                                        ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1 ;
+---------------------------------------+---------------+-----------------------------------------------------------------------------------------+
; Parameter Name                        ; Value         ; Type                                                                                    ;
+---------------------------------------+---------------+-----------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                     ; ON            ; AUTO_CARRY                                                                              ;
; IGNORE_CARRY_BUFFERS                  ; OFF           ; IGNORE_CARRY                                                                            ;
; AUTO_CASCADE_CHAINS                   ; ON            ; AUTO_CASCADE                                                                            ;
; IGNORE_CASCADE_BUFFERS                ; OFF           ; IGNORE_CASCADE                                                                          ;
; NUMBER_OF_MULTIPLIERS                 ; 1             ; Integer                                                                                 ;
; WIDTH_A                               ; 16            ; Integer                                                                                 ;
; WIDTH_B                               ; 16            ; Integer                                                                                 ;
; WIDTH_RESULT                          ; 32            ; Integer                                                                                 ;
; INPUT_REGISTER_A0                     ; UNREGISTERED  ; Untyped                                                                                 ;
; INPUT_ACLR_A0                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A0                       ; DATAA         ; Untyped                                                                                 ;
; INPUT_REGISTER_A1                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_A1                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A1                       ; DATAA         ; Untyped                                                                                 ;
; INPUT_REGISTER_A2                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_A2                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A2                       ; DATAA         ; Untyped                                                                                 ;
; INPUT_REGISTER_A3                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_A3                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A3                       ; DATAA         ; Untyped                                                                                 ;
; REPRESENTATION_A                      ; UNSIGNED      ; Untyped                                                                                 ;
; SIGNED_REGISTER_A                     ; UNREGISTERED  ; Untyped                                                                                 ;
; SIGNED_ACLR_A                         ; ACLR3         ; Untyped                                                                                 ;
; SIGNED_PIPELINE_REGISTER_A            ; CLOCK0        ; Untyped                                                                                 ;
; SIGNED_PIPELINE_ACLR_A                ; ACLR0         ; Untyped                                                                                 ;
; INPUT_REGISTER_B0                     ; UNREGISTERED  ; Untyped                                                                                 ;
; INPUT_ACLR_B0                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B0                       ; DATAB         ; Untyped                                                                                 ;
; INPUT_REGISTER_B1                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_B1                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B1                       ; DATAB         ; Untyped                                                                                 ;
; INPUT_REGISTER_B2                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_B2                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B2                       ; DATAB         ; Untyped                                                                                 ;
; INPUT_REGISTER_B3                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_B3                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B3                       ; DATAB         ; Untyped                                                                                 ;
; REPRESENTATION_B                      ; UNSIGNED      ; Untyped                                                                                 ;
; SIGNED_REGISTER_B                     ; UNREGISTERED  ; Untyped                                                                                 ;
; SIGNED_ACLR_B                         ; ACLR3         ; Untyped                                                                                 ;
; SIGNED_PIPELINE_REGISTER_B            ; CLOCK0        ; Untyped                                                                                 ;
; SIGNED_PIPELINE_ACLR_B                ; ACLR0         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER0                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR0                      ; ACLR0         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER1                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR1                      ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER1_DIRECTION                 ; ADD           ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_REGISTER1          ; UNREGISTERED  ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_ACLR1              ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR1     ; ACLR0         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER2                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR2                      ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER3                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR3                      ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER3_DIRECTION                 ; UNUSED        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_REGISTER3          ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_ACLR3              ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR3     ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER01_ROUNDING                 ; NO            ; Untyped                                                                                 ;
; MULTIPLIER01_SATURATION               ; NO            ; Untyped                                                                                 ;
; MULTIPLIER23_ROUNDING                 ; NO            ; Untyped                                                                                 ;
; MULTIPLIER23_SATURATION               ; NO            ; Untyped                                                                                 ;
; ADDER1_ROUNDING                       ; NO            ; Untyped                                                                                 ;
; ADDER3_ROUNDING                       ; NO            ; Untyped                                                                                 ;
; PORT_MULT0_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; PORT_MULT1_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; PORT_MULT2_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; PORT_MULT3_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; MULT01_ROUND_REGISTER                 ; CLOCK0        ; Untyped                                                                                 ;
; MULT01_ROUND_ACLR                     ; ACLR3         ; Untyped                                                                                 ;
; MULT23_ROUND_REGISTER                 ; CLOCK0        ; Untyped                                                                                 ;
; MULT23_ROUND_ACLR                     ; ACLR3         ; Untyped                                                                                 ;
; MULT01_SATURATION_REGISTER            ; CLOCK0        ; Untyped                                                                                 ;
; MULT01_SATURATION_ACLR                ; ACLR3         ; Untyped                                                                                 ;
; MULT23_SATURATION_REGISTER            ; CLOCK0        ; Untyped                                                                                 ;
; MULT23_SATURATION_ACLR                ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_REGISTER               ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_ACLR                   ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_PIPELINE_REGISTER      ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_PIPELINE_ACLR          ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_REGISTER               ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_ACLR                   ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_PIPELINE_REGISTER      ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_PIPELINE_ACLR          ; ACLR3         ; Untyped                                                                                 ;
; PORT_SIGNA                            ; PORT_UNUSED   ; Untyped                                                                                 ;
; PORT_SIGNB                            ; PORT_UNUSED   ; Untyped                                                                                 ;
; OUTPUT_REGISTER                       ; UNREGISTERED  ; Untyped                                                                                 ;
; OUTPUT_ACLR                           ; ACLR0         ; Untyped                                                                                 ;
; EXTRA_LATENCY                         ; 0             ; Untyped                                                                                 ;
; DEDICATED_MULTIPLIER_CIRCUITRY        ; YES           ; Untyped                                                                                 ;
; DSP_BLOCK_BALANCING                   ; AUTO          ; Untyped                                                                                 ;
; CBXI_PARAMETER                        ; mult_add_4cr2 ; Untyped                                                                                 ;
; DEVICE_FAMILY                         ; Cyclone II    ; Untyped                                                                                 ;
+---------------------------------------+---------------+-----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2 ;
+---------------------------------------+---------------+-----------------------------------------------------------------------------------------+
; Parameter Name                        ; Value         ; Type                                                                                    ;
+---------------------------------------+---------------+-----------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                     ; ON            ; AUTO_CARRY                                                                              ;
; IGNORE_CARRY_BUFFERS                  ; OFF           ; IGNORE_CARRY                                                                            ;
; AUTO_CASCADE_CHAINS                   ; ON            ; AUTO_CASCADE                                                                            ;
; IGNORE_CASCADE_BUFFERS                ; OFF           ; IGNORE_CASCADE                                                                          ;
; NUMBER_OF_MULTIPLIERS                 ; 1             ; Integer                                                                                 ;
; WIDTH_A                               ; 16            ; Integer                                                                                 ;
; WIDTH_B                               ; 16            ; Integer                                                                                 ;
; WIDTH_RESULT                          ; 16            ; Integer                                                                                 ;
; INPUT_REGISTER_A0                     ; UNREGISTERED  ; Untyped                                                                                 ;
; INPUT_ACLR_A0                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A0                       ; DATAA         ; Untyped                                                                                 ;
; INPUT_REGISTER_A1                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_A1                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A1                       ; DATAA         ; Untyped                                                                                 ;
; INPUT_REGISTER_A2                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_A2                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A2                       ; DATAA         ; Untyped                                                                                 ;
; INPUT_REGISTER_A3                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_A3                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_A3                       ; DATAA         ; Untyped                                                                                 ;
; REPRESENTATION_A                      ; UNSIGNED      ; Untyped                                                                                 ;
; SIGNED_REGISTER_A                     ; UNREGISTERED  ; Untyped                                                                                 ;
; SIGNED_ACLR_A                         ; ACLR3         ; Untyped                                                                                 ;
; SIGNED_PIPELINE_REGISTER_A            ; CLOCK0        ; Untyped                                                                                 ;
; SIGNED_PIPELINE_ACLR_A                ; ACLR0         ; Untyped                                                                                 ;
; INPUT_REGISTER_B0                     ; UNREGISTERED  ; Untyped                                                                                 ;
; INPUT_ACLR_B0                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B0                       ; DATAB         ; Untyped                                                                                 ;
; INPUT_REGISTER_B1                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_B1                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B1                       ; DATAB         ; Untyped                                                                                 ;
; INPUT_REGISTER_B2                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_B2                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B2                       ; DATAB         ; Untyped                                                                                 ;
; INPUT_REGISTER_B3                     ; CLOCK0        ; Untyped                                                                                 ;
; INPUT_ACLR_B3                         ; ACLR3         ; Untyped                                                                                 ;
; INPUT_SOURCE_B3                       ; DATAB         ; Untyped                                                                                 ;
; REPRESENTATION_B                      ; UNSIGNED      ; Untyped                                                                                 ;
; SIGNED_REGISTER_B                     ; UNREGISTERED  ; Untyped                                                                                 ;
; SIGNED_ACLR_B                         ; ACLR3         ; Untyped                                                                                 ;
; SIGNED_PIPELINE_REGISTER_B            ; CLOCK0        ; Untyped                                                                                 ;
; SIGNED_PIPELINE_ACLR_B                ; ACLR0         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER0                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR0                      ; ACLR0         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER1                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR1                      ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER1_DIRECTION                 ; ADD           ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_REGISTER1          ; UNREGISTERED  ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_ACLR1              ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR1     ; ACLR0         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER2                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR2                      ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER_REGISTER3                  ; CLOCK0        ; Untyped                                                                                 ;
; MULTIPLIER_ACLR3                      ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER3_DIRECTION                 ; UNUSED        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_REGISTER3          ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_ACLR3              ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3 ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB_MULTIPLIER_PIPELINE_ACLR3     ; ACLR3         ; Untyped                                                                                 ;
; MULTIPLIER01_ROUNDING                 ; NO            ; Untyped                                                                                 ;
; MULTIPLIER01_SATURATION               ; NO            ; Untyped                                                                                 ;
; MULTIPLIER23_ROUNDING                 ; NO            ; Untyped                                                                                 ;
; MULTIPLIER23_SATURATION               ; NO            ; Untyped                                                                                 ;
; ADDER1_ROUNDING                       ; NO            ; Untyped                                                                                 ;
; ADDER3_ROUNDING                       ; NO            ; Untyped                                                                                 ;
; PORT_MULT0_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; PORT_MULT1_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; PORT_MULT2_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; PORT_MULT3_IS_SATURATED               ; UNUSED        ; Untyped                                                                                 ;
; MULT01_ROUND_REGISTER                 ; CLOCK0        ; Untyped                                                                                 ;
; MULT01_ROUND_ACLR                     ; ACLR3         ; Untyped                                                                                 ;
; MULT23_ROUND_REGISTER                 ; CLOCK0        ; Untyped                                                                                 ;
; MULT23_ROUND_ACLR                     ; ACLR3         ; Untyped                                                                                 ;
; MULT01_SATURATION_REGISTER            ; CLOCK0        ; Untyped                                                                                 ;
; MULT01_SATURATION_ACLR                ; ACLR3         ; Untyped                                                                                 ;
; MULT23_SATURATION_REGISTER            ; CLOCK0        ; Untyped                                                                                 ;
; MULT23_SATURATION_ACLR                ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_REGISTER               ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_ACLR                   ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_PIPELINE_REGISTER      ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB1_ROUND_PIPELINE_ACLR          ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_REGISTER               ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_ACLR                   ; ACLR3         ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_PIPELINE_REGISTER      ; CLOCK0        ; Untyped                                                                                 ;
; ADDNSUB3_ROUND_PIPELINE_ACLR          ; ACLR3         ; Untyped                                                                                 ;
; PORT_SIGNA                            ; PORT_UNUSED   ; Untyped                                                                                 ;
; PORT_SIGNB                            ; PORT_UNUSED   ; Untyped                                                                                 ;
; OUTPUT_REGISTER                       ; UNREGISTERED  ; Untyped                                                                                 ;
; OUTPUT_ACLR                           ; ACLR0         ; Untyped                                                                                 ;
; EXTRA_LATENCY                         ; 0             ; Untyped                                                                                 ;
; DEDICATED_MULTIPLIER_CIRCUITRY        ; YES           ; Untyped                                                                                 ;
; DSP_BLOCK_BALANCING                   ; AUTO          ; Untyped                                                                                 ;
; CBXI_PARAMETER                        ; mult_add_6cr2 ; Untyped                                                                                 ;
; DEVICE_FAMILY                         ; Cyclone II    ; Untyped                                                                                 ;
+---------------------------------------+---------------+-----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component ;
+----------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value                             ; Type                                                                                                                                                                             ;
+----------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_file       ; cpu_0_ociram_default_contents.mif ; String                                                                                                                                                                           ;
+----------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram ;
+------------------------------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value                             ; Type                                                                                                                                                                                   ;
+------------------------------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                                 ; Untyped                                                                                                                                                                                ;
; AUTO_CARRY_CHAINS                  ; ON                                ; AUTO_CARRY                                                                                                                                                                             ;
; IGNORE_CARRY_BUFFERS               ; OFF                               ; IGNORE_CARRY                                                                                                                                                                           ;
; AUTO_CASCADE_CHAINS                ; ON                                ; AUTO_CASCADE                                                                                                                                                                           ;
; IGNORE_CASCADE_BUFFERS             ; OFF                               ; IGNORE_CASCADE                                                                                                                                                                         ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT                   ; Untyped                                                                                                                                                                                ;
; WIDTH_A                            ; 32                                ; Integer                                                                                                                                                                                ;
; WIDTHAD_A                          ; 8                                 ; Integer                                                                                                                                                                                ;
; NUMWORDS_A                         ; 256                               ; Integer                                                                                                                                                                                ;
; OUTDATA_REG_A                      ; UNREGISTERED                      ; Untyped                                                                                                                                                                                ;
; ADDRESS_ACLR_A                     ; NONE                              ; Untyped                                                                                                                                                                                ;
; OUTDATA_ACLR_A                     ; NONE                              ; Untyped                                                                                                                                                                                ;
; WRCONTROL_ACLR_A                   ; NONE                              ; Untyped                                                                                                                                                                                ;
; INDATA_ACLR_A                      ; NONE                              ; Untyped                                                                                                                                                                                ;
; BYTEENA_ACLR_A                     ; NONE                              ; Untyped                                                                                                                                                                                ;
; WIDTH_B                            ; 32                                ; Integer                                                                                                                                                                                ;
; WIDTHAD_B                          ; 8                                 ; Integer                                                                                                                                                                                ;
; NUMWORDS_B                         ; 256                               ; Integer                                                                                                                                                                                ;
; INDATA_REG_B                       ; CLOCK1                            ; Untyped                                                                                                                                                                                ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                            ; Untyped                                                                                                                                                                                ;
; RDCONTROL_REG_B                    ; CLOCK1                            ; Untyped                                                                                                                                                                                ;
; ADDRESS_REG_B                      ; CLOCK1                            ; Untyped                                                                                                                                                                                ;
; OUTDATA_REG_B                      ; UNREGISTERED                      ; Untyped                                                                                                                                                                                ;
; BYTEENA_REG_B                      ; CLOCK1                            ; Untyped                                                                                                                                                                                ;
; INDATA_ACLR_B                      ; NONE                              ; Untyped                                                                                                                                                                                ;
; WRCONTROL_ACLR_B                   ; NONE                              ; Untyped                                                                                                                                                                                ;
; ADDRESS_ACLR_B                     ; NONE                              ; Untyped                                                                                                                                                                                ;
; OUTDATA_ACLR_B                     ; NONE                              ; Untyped                                                                                                                                                                                ;
; RDCONTROL_ACLR_B                   ; NONE                              ; Untyped                                                                                                                                                                                ;
; BYTEENA_ACLR_B                     ; NONE                              ; Untyped                                                                                                                                                                                ;
; WIDTH_BYTEENA_A                    ; 4                                 ; Integer                                                                                                                                                                                ;
; WIDTH_BYTEENA_B                    ; 1                                 ; Untyped                                                                                                                                                                                ;
; RAM_BLOCK_TYPE                     ; AUTO                              ; Untyped                                                                                                                                                                                ;
; BYTE_SIZE                          ; 8                                 ; Untyped                                                                                                                                                                                ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA                          ; Untyped                                                                                                                                                                                ;
; INIT_FILE                          ; cpu_0_ociram_default_contents.mif ; Untyped                                                                                                                                                                                ;
; INIT_FILE_LAYOUT                   ; PORT_A                            ; Untyped                                                                                                                                                                                ;
; MAXIMUM_DEPTH                      ; 0                                 ; Untyped                                                                                                                                                                                ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                            ; Untyped                                                                                                                                                                                ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                            ; Untyped                                                                                                                                                                                ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                            ; Untyped                                                                                                                                                                                ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                            ; Untyped                                                                                                                                                                                ;
; DEVICE_FAMILY                      ; Cyclone II                        ; Untyped                                                                                                                                                                                ;
; CBXI_PARAMETER                     ; altsyncram_c572                   ; Untyped                                                                                                                                                                                ;
+------------------------------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component ;
+----------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value  ; Type                                                                                                                                                                                                            ;
+----------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_file       ; UNUSED ; String                                                                                                                                                                                                          ;
+----------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                     ; Value           ; Type                                                                                                                                                                                                         ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8               ; Untyped                                                                                                                                                                                                      ;
; AUTO_CARRY_CHAINS                  ; ON              ; AUTO_CARRY                                                                                                                                                                                                   ;
; IGNORE_CARRY_BUFFERS               ; OFF             ; IGNORE_CARRY                                                                                                                                                                                                 ;
; AUTO_CASCADE_CHAINS                ; ON              ; AUTO_CASCADE                                                                                                                                                                                                 ;
; IGNORE_CASCADE_BUFFERS             ; OFF             ; IGNORE_CASCADE                                                                                                                                                                                               ;
; OPERATION_MODE                     ; BIDIR_DUAL_PORT ; Untyped                                                                                                                                                                                                      ;
; WIDTH_A                            ; 36              ; Integer                                                                                                                                                                                                      ;
; WIDTHAD_A                          ; 7               ; Integer                                                                                                                                                                                                      ;
; NUMWORDS_A                         ; 128             ; Integer                                                                                                                                                                                                      ;
; OUTDATA_REG_A                      ; UNREGISTERED    ; Untyped                                                                                                                                                                                                      ;
; ADDRESS_ACLR_A                     ; NONE            ; Untyped                                                                                                                                                                                                      ;
; OUTDATA_ACLR_A                     ; NONE            ; Untyped                                                                                                                                                                                                      ;
; WRCONTROL_ACLR_A                   ; NONE            ; Untyped                                                                                                                                                                                                      ;
; INDATA_ACLR_A                      ; NONE            ; Untyped                                                                                                                                                                                                      ;
; BYTEENA_ACLR_A                     ; NONE            ; Untyped                                                                                                                                                                                                      ;
; WIDTH_B                            ; 36              ; Integer                                                                                                                                                                                                      ;
; WIDTHAD_B                          ; 7               ; Integer                                                                                                                                                                                                      ;
; NUMWORDS_B                         ; 128             ; Integer                                                                                                                                                                                                      ;
; INDATA_REG_B                       ; CLOCK1          ; Untyped                                                                                                                                                                                                      ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1          ; Untyped                                                                                                                                                                                                      ;
; RDCONTROL_REG_B                    ; CLOCK1          ; Untyped                                                                                                                                                                                                      ;
; ADDRESS_REG_B                      ; CLOCK1          ; Untyped                                                                                                                                                                                                      ;
; OUTDATA_REG_B                      ; UNREGISTERED    ; Untyped                                                                                                                                                                                                      ;
; BYTEENA_REG_B                      ; CLOCK1          ; Untyped                                                                                                                                                                                                      ;
; INDATA_ACLR_B                      ; NONE            ; Untyped                                                                                                                                                                                                      ;
; WRCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                                                                                                                                                      ;
; ADDRESS_ACLR_B                     ; NONE            ; Untyped                                                                                                                                                                                                      ;
; OUTDATA_ACLR_B                     ; NONE            ; Untyped                                                                                                                                                                                                      ;
; RDCONTROL_ACLR_B                   ; NONE            ; Untyped                                                                                                                                                                                                      ;
; BYTEENA_ACLR_B                     ; NONE            ; Untyped                                                                                                                                                                                                      ;
; WIDTH_BYTEENA_A                    ; 1               ; Untyped                                                                                                                                                                                                      ;
; WIDTH_BYTEENA_B                    ; 1               ; Untyped                                                                                                                                                                                                      ;
; RAM_BLOCK_TYPE                     ; AUTO            ; Untyped                                                                                                                                                                                                      ;
; BYTE_SIZE                          ; 8               ; Untyped                                                                                                                                                                                                      ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA        ; Untyped                                                                                                                                                                                                      ;
; INIT_FILE                          ; UNUSED          ; Untyped                                                                                                                                                                                                      ;
; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                                                                                                                                                                                      ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                                                                                                                                                                                                      ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                                                                                                                                                                                                      ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                                                                                                                                                                                      ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                                                                                                                                                                                      ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                                                                                                                                                                                      ;
; DEVICE_FAMILY                      ; Cyclone II      ; Untyped                                                                                                                                                                                                      ;
; CBXI_PARAMETER                     ; altsyncram_e502 ; Untyped                                                                                                                                                                                                      ;
+------------------------------------+-----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1 ;
+----------------+-----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value     ; Type                                                                                                                                                                                                     ;
+----------------+-----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SLD_NODE_INFO  ; 286279168 ; Integer                                                                                                                                                                                                  ;
+----------------+-----------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                    ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                              ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                            ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                            ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                          ;
; lpm_width               ; 8           ; Integer                                                                                                 ;
; LPM_NUMWORDS            ; 64          ; Integer                                                                                                 ;
; LPM_WIDTHU              ; 6           ; Integer                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                 ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                                                                 ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                                                                 ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                                 ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                 ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                                 ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                                 ;
; USE_EAB                 ; ON          ; Untyped                                                                                                 ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                 ;
; DEVICE_FAMILY           ; Cyclone II  ; Untyped                                                                                                 ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                                 ;
; CBXI_PARAMETER          ; scfifo_1n21 ; Untyped                                                                                                 ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------------------+
; Parameter Name          ; Value       ; Type                                                                                                    ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS       ; ON          ; AUTO_CARRY                                                                                              ;
; IGNORE_CARRY_BUFFERS    ; OFF         ; IGNORE_CARRY                                                                                            ;
; AUTO_CASCADE_CHAINS     ; ON          ; AUTO_CASCADE                                                                                            ;
; IGNORE_CASCADE_BUFFERS  ; OFF         ; IGNORE_CASCADE                                                                                          ;
; lpm_width               ; 8           ; Integer                                                                                                 ;
; LPM_NUMWORDS            ; 64          ; Integer                                                                                                 ;
; LPM_WIDTHU              ; 6           ; Integer                                                                                                 ;
; LPM_SHOWAHEAD           ; OFF         ; Untyped                                                                                                 ;
; UNDERFLOW_CHECKING      ; OFF         ; Untyped                                                                                                 ;
; OVERFLOW_CHECKING       ; OFF         ; Untyped                                                                                                 ;
; ALLOW_RWCYCLE_WHEN_FULL ; OFF         ; Untyped                                                                                                 ;
; ADD_RAM_OUTPUT_REGISTER ; OFF         ; Untyped                                                                                                 ;
; ALMOST_FULL_VALUE       ; 0           ; Untyped                                                                                                 ;
; ALMOST_EMPTY_VALUE      ; 0           ; Untyped                                                                                                 ;
; USE_EAB                 ; ON          ; Untyped                                                                                                 ;
; MAXIMIZE_SPEED          ; 5           ; Untyped                                                                                                 ;
; DEVICE_FAMILY           ; Cyclone II  ; Untyped                                                                                                 ;
; OPTIMIZE_FOR_SPEED      ; 5           ; Untyped                                                                                                 ;
; CBXI_PARAMETER          ; scfifo_1n21 ; Untyped                                                                                                 ;
+-------------------------+-------------+---------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic ;
+-------------------+----------------------------------+-------------------------------------------------------------------------------+
; Parameter Name    ; Value                            ; Type                                                                          ;
+-------------------+----------------------------------+-------------------------------------------------------------------------------+
; INSTANCE_ID       ; 0                                ; Integer                                                                       ;
; SLD_NODE_INFO     ; 00001100000000000110111000000000 ; Binary                                                                        ;
; LOG2_TXFIFO_DEPTH ; 6                                ; Integer                                                                       ;
; LOG2_RXFIFO_DEPTH ; 6                                ; Integer                                                                       ;
; RESERVED          ; 0                                ; Integer                                                                       ;
; DATA_WIDTH        ; 8                                ; Integer                                                                       ;
; NODE_IR_WIDTH     ; 1                                ; Integer                                                                       ;
; SCAN_LENGTH       ; 11                               ; Integer                                                                       ;
+-------------------+----------------------------------+-------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------+
; Parameter Settings for User Entity Instance: I2C_AV_Config:u1 ;
+----------------+----------+-----------------------------------+
; Parameter Name ; Value    ; Type                              ;
+----------------+----------+-----------------------------------+
; CLK_Freq       ; 50000000 ; Integer                           ;
; I2C_Freq       ; 20000    ; Integer                           ;
; LUT_SIZE       ; 51       ; Integer                           ;
; Dummy_DATA     ; 0        ; Integer                           ;
; SET_LIN_L      ; 1        ; Integer                           ;
; SET_LIN_R      ; 2        ; Integer                           ;
; SET_HEAD_L     ; 3        ; Integer                           ;
; SET_HEAD_R     ; 4        ; Integer                           ;
; A_PATH_CTRL    ; 5        ; Integer                           ;
; D_PATH_CTRL    ; 6        ; Integer                           ;
; POWER_ON       ; 7        ; Integer                           ;
; SET_FORMAT     ; 8        ; Integer                           ;
; SAMPLE_CTRL    ; 9        ; Integer                           ;
; SET_ACTIVE     ; 10       ; Integer                           ;
; SET_VIDEO      ; 11       ; Integer                           ;
+----------------+----------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst                                 ;
+--------------------------+------------------------------------------------------------------+---------+
; Parameter Name           ; Value                                                            ; Type    ;
+--------------------------+------------------------------------------------------------------+---------+
; sld_hub_ip_version       ; 1                                                                ; Untyped ;
; sld_hub_ip_minor_version ; 3                                                                ; Untyped ;
; sld_common_ip_version    ; 0                                                                ; Untyped ;
; device_family            ; Cyclone II                                                       ; Untyped ;
; n_nodes                  ; 2                                                                ; Untyped ;
; n_sel_bits               ; 2                                                                ; Untyped ;
; n_node_ir_bits           ; 5                                                                ; Untyped ;
; node_info                ; 0000110000000000011011100000000000010001000100000100011000000000 ; Binary  ;
; compilation_mode         ; 0                                                                ; Untyped ;
+--------------------------+------------------------------------------------------------------+---------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: I2C_AV_Config:u1|altsyncram:Ram0_rtl_0 ;
+------------------------------------+------------------------------+---------------------+
; Parameter Name                     ; Value                        ; Type                ;
+------------------------------------+------------------------------+---------------------+
; BYTE_SIZE_BLOCK                    ; 8                            ; Untyped             ;
; AUTO_CARRY_CHAINS                  ; ON                           ; AUTO_CARRY          ;
; IGNORE_CARRY_BUFFERS               ; OFF                          ; IGNORE_CARRY        ;
; AUTO_CASCADE_CHAINS                ; ON                           ; AUTO_CASCADE        ;
; IGNORE_CASCADE_BUFFERS             ; OFF                          ; IGNORE_CASCADE      ;
; OPERATION_MODE                     ; ROM                          ; Untyped             ;
; WIDTH_A                            ; 16                           ; Untyped             ;
; WIDTHAD_A                          ; 6                            ; Untyped             ;
; NUMWORDS_A                         ; 64                           ; Untyped             ;
; OUTDATA_REG_A                      ; UNREGISTERED                 ; Untyped             ;
; ADDRESS_ACLR_A                     ; NONE                         ; Untyped             ;
; OUTDATA_ACLR_A                     ; NONE                         ; Untyped             ;
; WRCONTROL_ACLR_A                   ; NONE                         ; Untyped             ;
; INDATA_ACLR_A                      ; NONE                         ; Untyped             ;
; BYTEENA_ACLR_A                     ; NONE                         ; Untyped             ;
; WIDTH_B                            ; 1                            ; Untyped             ;
; WIDTHAD_B                          ; 1                            ; Untyped             ;
; NUMWORDS_B                         ; 1                            ; Untyped             ;
; INDATA_REG_B                       ; CLOCK1                       ; Untyped             ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                       ; Untyped             ;
; RDCONTROL_REG_B                    ; CLOCK1                       ; Untyped             ;
; ADDRESS_REG_B                      ; CLOCK1                       ; Untyped             ;
; OUTDATA_REG_B                      ; UNREGISTERED                 ; Untyped             ;
; BYTEENA_REG_B                      ; CLOCK1                       ; Untyped             ;
; INDATA_ACLR_B                      ; NONE                         ; Untyped             ;
; WRCONTROL_ACLR_B                   ; NONE                         ; Untyped             ;
; ADDRESS_ACLR_B                     ; NONE                         ; Untyped             ;
; OUTDATA_ACLR_B                     ; NONE                         ; Untyped             ;
; RDCONTROL_ACLR_B                   ; NONE                         ; Untyped             ;
; BYTEENA_ACLR_B                     ; NONE                         ; Untyped             ;
; WIDTH_BYTEENA_A                    ; 1                            ; Untyped             ;
; WIDTH_BYTEENA_B                    ; 1                            ; Untyped             ;
; RAM_BLOCK_TYPE                     ; AUTO                         ; Untyped             ;
; BYTE_SIZE                          ; 8                            ; Untyped             ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                    ; Untyped             ;
; INIT_FILE                          ; DE2_NIOS_DEVICE_LED0.rtl.mif ; Untyped             ;
; INIT_FILE_LAYOUT                   ; PORT_A                       ; Untyped             ;
; MAXIMUM_DEPTH                      ; 0                            ; Untyped             ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                       ; Untyped             ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                       ; Untyped             ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                       ; Untyped             ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                       ; Untyped             ;
; DEVICE_FAMILY                      ; Cyclone II                   ; Untyped             ;
; CBXI_PARAMETER                     ; altsyncram_mj01              ; Untyped             ;
+------------------------------------+------------------------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------+
; altmult_add Parameter Settings by Entity Instance                                                                                          ;
+---------------------------------------+----------------------------------------------------------------------------------------------------+
; Name                                  ; Value                                                                                              ;
+---------------------------------------+----------------------------------------------------------------------------------------------------+
; Number of entity instances            ; 2                                                                                                  ;
; Entity Instance                       ; system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1 ;
;     -- NUMBER_OF_MULTIPLIERS          ; 1                                                                                                  ;
;     -- WIDTH_A                        ; 16                                                                                                 ;
;     -- WIDTH_B                        ; 16                                                                                                 ;
;     -- WIDTH_RESULT                   ; 32                                                                                                 ;
;     -- REPRESENTATION_A               ; UNSIGNED                                                                                           ;
;     -- REPRESENTATION_B               ; UNSIGNED                                                                                           ;
;     -- PORT_SIGNA                     ; PORT_UNUSED                                                                                        ;
;     -- PORT_SIGNB                     ; PORT_UNUSED                                                                                        ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                                                                                ;
; Entity Instance                       ; system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2 ;
;     -- NUMBER_OF_MULTIPLIERS          ; 1                                                                                                  ;
;     -- WIDTH_A                        ; 16                                                                                                 ;
;     -- WIDTH_B                        ; 16                                                                                                 ;
;     -- WIDTH_RESULT                   ; 16                                                                                                 ;
;     -- REPRESENTATION_A               ; UNSIGNED                                                                                           ;
;     -- REPRESENTATION_B               ; UNSIGNED                                                                                           ;
;     -- PORT_SIGNA                     ; PORT_UNUSED                                                                                        ;
;     -- PORT_SIGNB                     ; PORT_UNUSED                                                                                        ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                                                                                ;
+---------------------------------------+----------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; scfifo Parameter Settings by Entity Instance                                                                                    ;
+----------------------------+----------------------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                              ;
+----------------------------+----------------------------------------------------------------------------------------------------+
; Number of entity instances ; 2                                                                                                  ;
; Entity Instance            ; system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo ;
;     -- FIFO Type           ; Single Clock                                                                                       ;
;     -- lpm_width           ; 8                                                                                                  ;
;     -- LPM_NUMWORDS        ; 64                                                                                                 ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                ;
;     -- USE_EAB             ; ON                                                                                                 ;
; Entity Instance            ; system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo ;
;     -- FIFO Type           ; Single Clock                                                                                       ;
;     -- lpm_width           ; 8                                                                                                  ;
;     -- LPM_NUMWORDS        ; 64                                                                                                 ;
;     -- LPM_SHOWAHEAD       ; OFF                                                                                                ;
;     -- USE_EAB             ; ON                                                                                                 ;
+----------------------------+----------------------------------------------------------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Sun Apr 08 00:50:55 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_NIOS_DEVICE_LED -c DE2_NIOS_DEVICE_LED
Info: Found 1 design units, including 1 entities, in source file Audio_0.v
    Info: Found entity 1: Audio_0
Info: Found 1 design units, including 1 entities, in source file AUDIO_DAC_FIFO.v
    Info: Found entity 1: AUDIO_DAC_FIFO
Info: Found 1 design units, including 1 entities, in source file Audio_PLL.v
    Info: Found entity 1: Audio_PLL
Info: Found 1 design units, including 1 entities, in source file button_pio.v
    Info: Found entity 1: button_pio
Info: Found 29 design units, including 29 entities, in source file cpu_0.v
    Info: Found entity 1: cpu_0_ic_data_module
    Info: Found entity 2: cpu_0_ic_tag_module
    Info: Found entity 3: cpu_0_bht_module
    Info: Found entity 4: cpu_0_register_bank_a_module
    Info: Found entity 5: cpu_0_register_bank_b_module
    Info: Found entity 6: cpu_0_dc_tag_module
    Info: Found entity 7: cpu_0_dc_data_module
    Info: Found entity 8: cpu_0_nios2_oci_debug
    Info: Found entity 9: cpu_0_ociram_lpm_dram_bdp_component_module
    Info: Found entity 10: cpu_0_nios2_ocimem
    Info: Found entity 11: cpu_0_nios2_avalon_reg
    Info: Found entity 12: cpu_0_nios2_oci_break
    Info: Found entity 13: cpu_0_nios2_oci_xbrk
    Info: Found entity 14: cpu_0_nios2_oci_match_paired
    Info: Found entity 15: cpu_0_nios2_oci_match_single
    Info: Found entity 16: cpu_0_nios2_oci_dbrk
    Info: Found entity 17: cpu_0_nios2_oci_itrace
    Info: Found entity 18: cpu_0_nios2_oci_td_mode
    Info: Found entity 19: cpu_0_nios2_oci_dtrace
    Info: Found entity 20: cpu_0_nios2_oci_compute_tm_count
    Info: Found entity 21: cpu_0_nios2_oci_fifowp_inc
    Info: Found entity 22: cpu_0_nios2_oci_fifocount_inc
    Info: Found entity 23: cpu_0_nios2_oci_fifo
    Info: Found entity 24: cpu_0_nios2_oci_pib
    Info: Found entity 25: cpu_0_traceram_lpm_dram_bdp_component_module
    Info: Found entity 26: cpu_0_nios2_oci_im
    Info: Found entity 27: cpu_0_nios2_performance_monitors
    Info: Found entity 28: cpu_0_nios2_oci
    Info: Found entity 29: cpu_0
Info: Found 1 design units, including 1 entities, in source file cpu_0_jtag_debug_module.v
    Info: Found entity 1: cpu_0_jtag_debug_module
Info: Found 1 design units, including 1 entities, in source file cpu_0_jtag_debug_module_wrapper.v
    Info: Found entity 1: cpu_0_jtag_debug_module_wrapper
Info: Found 1 design units, including 1 entities, in source file cpu_0_mult_cell.v
    Info: Found entity 1: cpu_0_mult_cell
Info: Found 1 design units, including 1 entities, in source file cpu_0_test_bench.v
    Info: Found entity 1: cpu_0_test_bench
Info: Found 1 design units, including 1 entities, in source file DE2_NIOS_DEVICE_LED.v
    Info: Found entity 1: DE2_NIOS_DEVICE_LED
Info: Found 1 design units, including 1 entities, in source file DM9000A.v
    Info: Found entity 1: DM9000A
Info: Found 1 design units, including 1 entities, in source file DM9000A_IF.v
    Info: Found entity 1: DM9000A_IF
Info: Found 3 design units, including 3 entities, in source file epcs_controller.v
    Info: Found entity 1: epcs_controller_sub
    Info: Found entity 2: tornado_epcs_controller_atom
    Info: Found entity 3: epcs_controller
Info: Found 1 design units, including 1 entities, in source file FIFO_16_256.v
    Info: Found entity 1: FIFO_16_256
Info: Found 1 design units, including 1 entities, in source file I2C_AV_Config.v
    Info: Found entity 1: I2C_AV_Config
Info: Found 1 design units, including 1 entities, in source file I2C_Controller.v
    Info: Found entity 1: I2C_Controller
Info: Found 1 design units, including 1 entities, in source file Img_RAM.v
    Info: Found entity 1: Img_RAM
Info: Found 1 design units, including 1 entities, in source file ISP1362.v
    Info: Found entity 1: ISP1362
Info: Found 1 design units, including 1 entities, in source file ISP1362_IF.v
    Info: Found entity 1: ISP1362_IF
Info: Found 7 design units, including 7 entities, in source file jtag_uart_0.v
    Info: Found entity 1: jtag_uart_0_log_module
    Info: Found entity 2: jtag_uart_0_sim_scfifo_w
    Info: Found entity 3: jtag_uart_0_scfifo_w
    Info: Found entity 4: jtag_uart_0_drom_module
    Info: Found entity 5: jtag_uart_0_sim_scfifo_r
    Info: Found entity 6: jtag_uart_0_scfifo_r
    Info: Found entity 7: jtag_uart_0
Info: Found 1 design units, including 1 entities, in source file lcd_16207_0.v
    Info: Found entity 1: lcd_16207_0
Info: Found 1 design units, including 1 entities, in source file led_green.v
    Info: Found entity 1: led_green
Info: Found 1 design units, including 1 entities, in source file led_red.v
    Info: Found entity 1: led_red
Info: Found 1 design units, including 1 entities, in source file Reset_Delay.v
    Info: Found entity 1: Reset_Delay
Info: Found 1 design units, including 1 entities, in source file SD_CLK.v
    Info: Found entity 1: SD_CLK
Info: Found 1 design units, including 1 entities, in source file SD_CMD.v
    Info: Found entity 1: SD_CMD
Info: Found 1 design units, including 1 entities, in source file SD_DAT.v
    Info: Found entity 1: SD_DAT
Info: Found 2 design units, including 2 entities, in source file sdram_0.v
    Info: Found entity 1: sdram_0_input_efifo_module
    Info: Found entity 2: sdram_0
Info: Found 2 design units, including 2 entities, in source file sdram_0_test_component.v
    Info: Found entity 1: sdram_0_test_component_ram_module
    Info: Found entity 2: sdram_0_test_component
Info: Found 1 design units, including 1 entities, in source file SDRAM_PLL.v
    Info: Found entity 1: SDRAM_PLL
Info: Found 1 design units, including 1 entities, in source file SEG7_Display.v
    Info: Found entity 1: SEG7_Display
Info: Found 1 design units, including 1 entities, in source file SEG7_LUT.v
    Info: Found entity 1: SEG7_LUT
Info: Found 1 design units, including 1 entities, in source file SEG7_LUT_8.v
    Info: Found entity 1: SEG7_LUT_8
Info: Found 1 design units, including 1 entities, in source file sram_0.v
    Info: Found entity 1: sram_0
Info: Found 1 design units, including 1 entities, in source file SRAM_16Bit_512K.v
    Info: Found entity 1: SRAM_16Bit_512K
Info: Found 1 design units, including 1 entities, in source file switch_pio.v
    Info: Found entity 1: switch_pio
Info: Found 22 design units, including 22 entities, in source file system_0.v
    Info: Found entity 1: button_pio_s1_arbitrator
    Info: Found entity 2: clock_0_in_arbitrator
    Info: Found entity 3: clock_0_out_arbitrator
    Info: Found entity 4: clock_1_in_arbitrator
    Info: Found entity 5: clock_1_out_arbitrator
    Info: Found entity 6: cpu_0_jtag_debug_module_arbitrator
    Info: Found entity 7: cpu_0_data_master_arbitrator
    Info: Found entity 8: cpu_0_instruction_master_arbitrator
    Info: Found entity 9: jtag_uart_0_avalon_jtag_slave_arbitrator
    Info: Found entity 10: rdv_fifo_for_clock_0_out_to_sdram_0_s1_module
    Info: Found entity 11: rdv_fifo_for_clock_1_out_to_sdram_0_s1_module
    Info: Found entity 12: sdram_0_s1_arbitrator
    Info: Found entity 13: sram_0_avalon_slave_0_arbitrator
    Info: Found entity 14: timer_0_s1_arbitrator
    Info: Found entity 15: timer_1_s1_arbitrator
    Info: Found entity 16: tri_state_bridge_0_avalon_slave_arbitrator
    Info: Found entity 17: tri_state_bridge_0_bridge_arbitrator
    Info: Found entity 18: system_0_reset_clk_domain_synch_module
    Info: Found entity 19: system_0_reset_clk_50_domain_synch_module
    Info: Found entity 20: system_0
    Info: Found entity 21: cfi_flash_0_lane0_module
    Info: Found entity 22: cfi_flash_0
Info: Found 1 design units, including 1 entities, in source file timer_0.v
    Info: Found entity 1: timer_0
Info: Found 1 design units, including 1 entities, in source file timer_1.v
    Info: Found entity 1: timer_1
Info: Found 7 design units, including 7 entities, in source file uart_0.v
    Info: Found entity 1: uart_0_log_module
    Info: Found entity 2: uart_0_tx
    Info: Found entity 3: uart_0_rx_stimulus_source_character_source_rom_module
    Info: Found entity 4: uart_0_rx_stimulus_source
    Info: Found entity 5: uart_0_rx
    Info: Found entity 6: uart_0_regs
    Info: Found entity 7: uart_0
Info: Found 1 design units, including 1 entities, in source file VGA_0.v
    Info: Found entity 1: VGA_0
Info: Found 1 design units, including 1 entities, in source file VGA_Controller.v
    Info: Found entity 1: VGA_Controller
Info: Found 1 design units, including 1 entities, in source file VGA_NIOS_CTRL.v
    Info: Found entity 1: VGA_NIOS_CTRL
Info: Found 1 design units, including 1 entities, in source file VGA_OSD_RAM.v
    Info: Found entity 1: VGA_OSD_RAM
Info: Elaborating entity "DE2_NIOS_DEVICE_LED" for the top level hierarchy
Warning (10034): Output port "HEX0[6]" at DE2_NIOS_DEVICE_LED.v(181) has no driver
Warning (10034): Output port "HEX0[5]" at DE2_NIOS_DEVICE_LED.v(181) has no driver
Warning (10034): Output port "HEX0[4]" at DE2_NIOS_DEVICE_LED.v(181) has no driver
Warning (10034): Output port "HEX0[3]" at DE2_NIOS_DEVICE_LED.v(181) has no driver
Warning (10034): Output port "HEX0[2]" at DE2_NIOS_DEVICE_LED.v(181) has no driver
Warning (10034): Output port "HEX0[1]" at DE2_NIOS_DEVICE_LED.v(181) has no driver
Warning (10034): Output port "HEX0[0]" at DE2_NIOS_DEVICE_LED.v(181) has no driver
Warning (10034): Output port "HEX1[6]" at DE2_NIOS_DEVICE_LED.v(182) has no driver
Warning (10034): Output port "HEX1[5]" at DE2_NIOS_DEVICE_LED.v(182) has no driver
Warning (10034): Output port "HEX1[4]" at DE2_NIOS_DEVICE_LED.v(182) has no driver
Warning (10034): Output port "HEX1[3]" at DE2_NIOS_DEVICE_LED.v(182) has no driver
Warning (10034): Output port "HEX1[2]" at DE2_NIOS_DEVICE_LED.v(182) has no driver
Warning (10034): Output port "HEX1[1]" at DE2_NIOS_DEVICE_LED.v(182) has no driver
Warning (10034): Output port "HEX1[0]" at DE2_NIOS_DEVICE_LED.v(182) has no driver
Warning (10034): Output port "HEX2[6]" at DE2_NIOS_DEVICE_LED.v(183) has no driver
Warning (10034): Output port "HEX2[5]" at DE2_NIOS_DEVICE_LED.v(183) has no driver
Warning (10034): Output port "HEX2[4]" at DE2_NIOS_DEVICE_LED.v(183) has no driver
Warning (10034): Output port "HEX2[3]" at DE2_NIOS_DEVICE_LED.v(183) has no driver
Warning (10034): Output port "HEX2[2]" at DE2_NIOS_DEVICE_LED.v(183) has no driver
Warning (10034): Output port "HEX2[1]" at DE2_NIOS_DEVICE_LED.v(183) has no driver
Warning (10034): Output port "HEX2[0]" at DE2_NIOS_DEVICE_LED.v(183) has no driver
Warning (10034): Output port "HEX3[6]" at DE2_NIOS_DEVICE_LED.v(184) has no driver
Warning (10034): Output port "HEX3[5]" at DE2_NIOS_DEVICE_LED.v(184) has no driver
Warning (10034): Output port "HEX3[4]" at DE2_NIOS_DEVICE_LED.v(184) has no driver
Warning (10034): Output port "HEX3[3]" at DE2_NIOS_DEVICE_LED.v(184) has no driver
Warning (10034): Output port "HEX3[2]" at DE2_NIOS_DEVICE_LED.v(184) has no driver
Warning (10034): Output port "HEX3[1]" at DE2_NIOS_DEVICE_LED.v(184) has no driver
Warning (10034): Output port "HEX3[0]" at DE2_NIOS_DEVICE_LED.v(184) has no driver
Warning (10034): Output port "HEX4[6]" at DE2_NIOS_DEVICE_LED.v(185) has no driver
Warning (10034): Output port "HEX4[5]" at DE2_NIOS_DEVICE_LED.v(185) has no driver
Warning (10034): Output port "HEX4[4]" at DE2_NIOS_DEVICE_LED.v(185) has no driver
Warning (10034): Output port "HEX4[3]" at DE2_NIOS_DEVICE_LED.v(185) has no driver
Warning (10034): Output port "HEX4[2]" at DE2_NIOS_DEVICE_LED.v(185) has no driver
Warning (10034): Output port "HEX4[1]" at DE2_NIOS_DEVICE_LED.v(185) has no driver
Warning (10034): Output port "HEX4[0]" at DE2_NIOS_DEVICE_LED.v(185) has no driver
Warning (10034): Output port "HEX5[6]" at DE2_NIOS_DEVICE_LED.v(186) has no driver
Warning (10034): Output port "HEX5[5]" at DE2_NIOS_DEVICE_LED.v(186) has no driver
Warning (10034): Output port "HEX5[4]" at DE2_NIOS_DEVICE_LED.v(186) has no driver
Warning (10034): Output port "HEX5[3]" at DE2_NIOS_DEVICE_LED.v(186) has no driver
Warning (10034): Output port "HEX5[2]" at DE2_NIOS_DEVICE_LED.v(186) has no driver
Warning (10034): Output port "HEX5[1]" at DE2_NIOS_DEVICE_LED.v(186) has no driver
Warning (10034): Output port "HEX5[0]" at DE2_NIOS_DEVICE_LED.v(186) has no driver
Warning (10034): Output port "HEX6[6]" at DE2_NIOS_DEVICE_LED.v(187) has no driver
Warning (10034): Output port "HEX6[5]" at DE2_NIOS_DEVICE_LED.v(187) has no driver
Warning (10034): Output port "HEX6[4]" at DE2_NIOS_DEVICE_LED.v(187) has no driver
Warning (10034): Output port "HEX6[3]" at DE2_NIOS_DEVICE_LED.v(187) has no driver
Warning (10034): Output port "HEX6[2]" at DE2_NIOS_DEVICE_LED.v(187) has no driver
Warning (10034): Output port "HEX6[1]" at DE2_NIOS_DEVICE_LED.v(187) has no driver
Warning (10034): Output port "HEX6[0]" at DE2_NIOS_DEVICE_LED.v(187) has no driver
Warning (10034): Output port "HEX7[6]" at DE2_NIOS_DEVICE_LED.v(188) has no driver
Warning (10034): Output port "HEX7[5]" at DE2_NIOS_DEVICE_LED.v(188) has no driver
Warning (10034): Output port "HEX7[4]" at DE2_NIOS_DEVICE_LED.v(188) has no driver
Warning (10034): Output port "HEX7[3]" at DE2_NIOS_DEVICE_LED.v(188) has no driver
Warning (10034): Output port "HEX7[2]" at DE2_NIOS_DEVICE_LED.v(188) has no driver
Warning (10034): Output port "HEX7[1]" at DE2_NIOS_DEVICE_LED.v(188) has no driver
Warning (10034): Output port "HEX7[0]" at DE2_NIOS_DEVICE_LED.v(188) has no driver
Warning (10034): Output port "LEDG[8]" at DE2_NIOS_DEVICE_LED.v(190) has no driver
Warning (10034): Output port "LEDG[7]" at DE2_NIOS_DEVICE_LED.v(190) has no driver
Warning (10034): Output port "LEDG[6]" at DE2_NIOS_DEVICE_LED.v(190) has no driver
Warning (10034): Output port "LEDG[5]" at DE2_NIOS_DEVICE_LED.v(190) has no driver
Warning (10034): Output port "LEDG[4]" at DE2_NIOS_DEVICE_LED.v(190) has no driver
Warning (10034): Output port "LEDG[3]" at DE2_NIOS_DEVICE_LED.v(190) has no driver
Warning (10034): Output port "LEDG[2]" at DE2_NIOS_DEVICE_LED.v(190) has no driver
Warning (10034): Output port "LEDG[1]" at DE2_NIOS_DEVICE_LED.v(190) has no driver
Warning (10034): Output port "LEDG[0]" at DE2_NIOS_DEVICE_LED.v(190) has no driver
Warning (10034): Output port "LEDR[17]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[16]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[15]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[14]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[13]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[12]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[11]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[10]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[9]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[8]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[7]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[6]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[5]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[4]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[3]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[2]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[1]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "LEDR[0]" at DE2_NIOS_DEVICE_LED.v(191) has no driver
Warning (10034): Output port "UART_TXD" at DE2_NIOS_DEVICE_LED.v(193) has no driver
Warning (10034): Output port "IRDA_TXD" at DE2_NIOS_DEVICE_LED.v(196) has no driver
Warning (10034): Output port "OTG_ADDR[1]" at DE2_NIOS_DEVICE_LED.v(228) has no driver
Warning (10034): Output port "OTG_ADDR[0]" at DE2_NIOS_DEVICE_LED.v(228) has no driver
Warning (10034): Output port "OTG_CS_N" at DE2_NIOS_DEVICE_LED.v(229) has no driver
Warning (10034): Output port "OTG_RD_N" at DE2_NIOS_DEVICE_LED.v(230) has no driver
Warning (10034): Output port "OTG_WR_N" at DE2_NIOS_DEVICE_LED.v(231) has no driver
Warning (10034): Output port "OTG_RST_N" at DE2_NIOS_DEVICE_LED.v(232) has no driver
Warning (10034): Output port "OTG_DACK0_N" at DE2_NIOS_DEVICE_LED.v(239) has no driver
Warning (10034): Output port "OTG_DACK1_N" at DE2_NIOS_DEVICE_LED.v(240) has no driver
Warning (10034): Output port "LCD_RW" at DE2_NIOS_DEVICE_LED.v(245) has no driver
Warning (10034): Output port "LCD_EN" at DE2_NIOS_DEVICE_LED.v(246) has no driver
Warning (10034): Output port "LCD_RS" at DE2_NIOS_DEVICE_LED.v(247) has no driver
Warning (10034): Output port "SD_CLK" at DE2_NIOS_DEVICE_LED.v(252) has no driver
Warning (10034): Output port "TDO" at DE2_NIOS_DEVICE_LED.v(263) has no driver
Warning (10034): Output port "VGA_CLK" at DE2_NIOS_DEVICE_LED.v(265) has no driver
Warning (10034): Output port "VGA_HS" at DE2_NIOS_DEVICE_LED.v(266) has no driver
Warning (10034): Output port "VGA_VS" at DE2_NIOS_DEVICE_LED.v(267) has no driver
Warning (10034): Output port "VGA_BLANK" at DE2_NIOS_DEVICE_LED.v(268) has no driver
Warning (10034): Output port "VGA_SYNC" at DE2_NIOS_DEVICE_LED.v(269) has no driver
Warning (10034): Output port "VGA_R[9]" at DE2_NIOS_DEVICE_LED.v(270) has no driver
Warning (10034): Output port "VGA_R[8]" at DE2_NIOS_DEVICE_LED.v(270) has no driver
Warning (10034): Output port "VGA_R[7]" at DE2_NIOS_DEVICE_LED.v(270) has no driver
Warning (10034): Output port "VGA_R[6]" at DE2_NIOS_DEVICE_LED.v(270) has no driver
Warning (10034): Output port "VGA_R[5]" at DE2_NIOS_DEVICE_LED.v(270) has no driver
Warning (10034): Output port "VGA_R[4]" at DE2_NIOS_DEVICE_LED.v(270) has no driver
Warning (10034): Output port "VGA_R[3]" at DE2_NIOS_DEVICE_LED.v(270) has no driver
Warning (10034): Output port "VGA_R[2]" at DE2_NIOS_DEVICE_LED.v(270) has no driver
Warning (10034): Output port "VGA_R[1]" at DE2_NIOS_DEVICE_LED.v(270) has no driver
Warning (10034): Output port "VGA_R[0]" at DE2_NIOS_DEVICE_LED.v(270) has no driver
Warning (10034): Output port "VGA_G[9]" at DE2_NIOS_DEVICE_LED.v(271) has no driver
Warning (10034): Output port "VGA_G[8]" at DE2_NIOS_DEVICE_LED.v(271) has no driver
Warning (10034): Output port "VGA_G[7]" at DE2_NIOS_DEVICE_LED.v(271) has no driver
Warning (10034): Output port "VGA_G[6]" at DE2_NIOS_DEVICE_LED.v(271) has no driver
Warning (10034): Output port "VGA_G[5]" at DE2_NIOS_DEVICE_LED.v(271) has no driver
Warning (10034): Output port "VGA_G[4]" at DE2_NIOS_DEVICE_LED.v(271) has no driver
Warning (10034): Output port "VGA_G[3]" at DE2_NIOS_DEVICE_LED.v(271) has no driver
Warning (10034): Output port "VGA_G[2]" at DE2_NIOS_DEVICE_LED.v(271) has no driver
Warning (10034): Output port "VGA_G[1]" at DE2_NIOS_DEVICE_LED.v(271) has no driver
Warning (10034): Output port "VGA_G[0]" at DE2_NIOS_DEVICE_LED.v(271) has no driver
Warning (10034): Output port "VGA_B[9]" at DE2_NIOS_DEVICE_LED.v(272) has no driver
Warning (10034): Output port "VGA_B[8]" at DE2_NIOS_DEVICE_LED.v(272) has no driver
Warning (10034): Output port "VGA_B[7]" at DE2_NIOS_DEVICE_LED.v(272) has no driver
Warning (10034): Output port "VGA_B[6]" at DE2_NIOS_DEVICE_LED.v(272) has no driver
Warning (10034): Output port "VGA_B[5]" at DE2_NIOS_DEVICE_LED.v(272) has no driver
Warning (10034): Output port "VGA_B[4]" at DE2_NIOS_DEVICE_LED.v(272) has no driver
Warning (10034): Output port "VGA_B[3]" at DE2_NIOS_DEVICE_LED.v(272) has no driver
Warning (10034): Output port "VGA_B[2]" at DE2_NIOS_DEVICE_LED.v(272) has no driver
Warning (10034): Output port "VGA_B[1]" at DE2_NIOS_DEVICE_LED.v(272) has no driver
Warning (10034): Output port "VGA_B[0]" at DE2_NIOS_DEVICE_LED.v(272) has no driver
Warning (10034): Output port "ENET_CMD" at DE2_NIOS_DEVICE_LED.v(275) has no driver
Warning (10034): Output port "ENET_CS_N" at DE2_NIOS_DEVICE_LED.v(276) has no driver
Warning (10034): Output port "ENET_WR_N" at DE2_NIOS_DEVICE_LED.v(277) has no driver
Warning (10034): Output port "ENET_RD_N" at DE2_NIOS_DEVICE_LED.v(278) has no driver
Warning (10034): Output port "ENET_RST_N" at DE2_NIOS_DEVICE_LED.v(279) has no driver
Warning (10034): Output port "ENET_CLK" at DE2_NIOS_DEVICE_LED.v(281) has no driver
Warning (10034): Output port "AUD_DACDAT" at DE2_NIOS_DEVICE_LED.v(286) has no driver
Warning (10034): Output port "AUD_XCK" at DE2_NIOS_DEVICE_LED.v(288) has no driver
Warning (10665): Bidirectional port "AUD_DACLRCK" at DE2_NIOS_DEVICE_LED.v(285) has a one-way connection to bidirectional port "AUD_ADCLRCK"
Info: Elaborating entity "Reset_Delay" for hierarchy "Reset_Delay:delay1"
Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(18): truncated value with size 32 to match size of target (24)
Info: Elaborating entity "SDRAM_PLL" for hierarchy "SDRAM_PLL:PLL1"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "SDRAM_PLL:PLL1|altpll:altpll_component"
Info: Elaborated megafunction instantiation "SDRAM_PLL:PLL1|altpll:altpll_component"
Info: Elaborating entity "Audio_PLL" for hierarchy "Audio_PLL:PLL2"
Info: Elaborating entity "altpll" for hierarchy "Audio_PLL:PLL2|altpll:altpll_component"
Info: Elaborated megafunction instantiation "Audio_PLL:PLL2|altpll:altpll_component"
Info: Elaborating entity "system_0" for hierarchy "system_0:u0"
Info: Elaborating entity "button_pio_s1_arbitrator" for hierarchy "system_0:u0|button_pio_s1_arbitrator:the_button_pio_s1"
Info: Elaborating entity "button_pio" for hierarchy "system_0:u0|button_pio:the_button_pio"
Info: Elaborating entity "clock_0_in_arbitrator" for hierarchy "system_0:u0|clock_0_in_arbitrator:the_clock_0_in"
Info: Elaborating entity "clock_0_out_arbitrator" for hierarchy "system_0:u0|clock_0_out_arbitrator:the_clock_0_out"
Warning: Using design file clock_0.v, which is not specified as a design file for the current project, but contains definitions for 9 design units and 9 entities in project
    Info: Found entity 1: clock_0_master_read_done_sync_module
    Info: Found entity 2: clock_0_master_write_done_sync_module
    Info: Found entity 3: clock_0_edge_to_pulse
    Info: Found entity 4: clock_0_slave_FSM
    Info: Found entity 5: clock_0_slave_read_request_sync_module
    Info: Found entity 6: clock_0_slave_write_request_sync_module
    Info: Found entity 7: clock_0_master_FSM
    Info: Found entity 8: clock_0_bit_pipe
    Info: Found entity 9: clock_0
Info: Elaborating entity "clock_0" for hierarchy "system_0:u0|clock_0:the_clock_0"
Info: Elaborating entity "clock_0_master_read_done_sync_module" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync"
Info: Elaborating entity "clock_0_master_write_done_sync_module" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync"
Info: Elaborating entity "clock_0_edge_to_pulse" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse"
Info: Elaborating entity "clock_0_slave_FSM" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM"
Info: Elaborating entity "clock_0_slave_read_request_sync_module" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync"
Info: Elaborating entity "clock_0_slave_write_request_sync_module" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync"
Info: Elaborating entity "clock_0_master_FSM" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM"
Info: Elaborating entity "clock_0_bit_pipe" for hierarchy "system_0:u0|clock_0:the_clock_0|clock_0_bit_pipe:endofpacket_bit_pipe"
Info: Elaborating entity "clock_1_in_arbitrator" for hierarchy "system_0:u0|clock_1_in_arbitrator:the_clock_1_in"
Info: Elaborating entity "clock_1_out_arbitrator" for hierarchy "system_0:u0|clock_1_out_arbitrator:the_clock_1_out"
Warning: Using design file clock_1.v, which is not specified as a design file for the current project, but contains definitions for 9 design units and 9 entities in project
    Info: Found entity 1: clock_1_master_read_done_sync_module
    Info: Found entity 2: clock_1_master_write_done_sync_module
    Info: Found entity 3: clock_1_edge_to_pulse
    Info: Found entity 4: clock_1_slave_FSM
    Info: Found entity 5: clock_1_slave_read_request_sync_module
    Info: Found entity 6: clock_1_slave_write_request_sync_module
    Info: Found entity 7: clock_1_master_FSM
    Info: Found entity 8: clock_1_bit_pipe
    Info: Found entity 9: clock_1
Info: Elaborating entity "clock_1" for hierarchy "system_0:u0|clock_1:the_clock_1"
Info: Elaborating entity "clock_1_master_read_done_sync_module" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync"
Info: Elaborating entity "clock_1_master_write_done_sync_module" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync"
Info: Elaborating entity "clock_1_edge_to_pulse" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_edge_to_pulse:read_done_edge_to_pulse"
Info: Elaborating entity "clock_1_slave_FSM" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM"
Info: Elaborating entity "clock_1_slave_read_request_sync_module" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync"
Info: Elaborating entity "clock_1_slave_write_request_sync_module" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync"
Info: Elaborating entity "clock_1_master_FSM" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM"
Info: Elaborating entity "clock_1_bit_pipe" for hierarchy "system_0:u0|clock_1:the_clock_1|clock_1_bit_pipe:endofpacket_bit_pipe"
Info: Elaborating entity "cpu_0_jtag_debug_module_arbitrator" for hierarchy "system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module"
Info: Elaborating entity "cpu_0_data_master_arbitrator" for hierarchy "system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master"
Info: Elaborating entity "cpu_0_instruction_master_arbitrator" for hierarchy "system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master"
Info: Elaborating entity "cpu_0" for hierarchy "system_0:u0|cpu_0:the_cpu_0"
Info: Elaborating entity "cpu_0_test_bench" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench"
Info: Elaborating entity "cpu_0_ic_data_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_cub1.tdf
    Info: Found entity 1: altsyncram_cub1
Info: Elaborating entity "altsyncram_cub1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_k1l1.tdf
    Info: Found entity 1: altsyncram_k1l1
Info: Elaborating entity "altsyncram_k1l1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1"
Info: Elaborating entity "cpu_0_ic_tag_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_tke1.tdf
    Info: Found entity 1: altsyncram_tke1
Info: Elaborating entity "altsyncram_tke1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_tke1:auto_generated"
Info: Elaborating entity "cpu_0_bht_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_q8e1.tdf
    Info: Found entity 1: altsyncram_q8e1
Info: Elaborating entity "altsyncram_q8e1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pfn1.tdf
    Info: Found entity 1: altsyncram_pfn1
Info: Elaborating entity "altsyncram_pfn1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated|altsyncram_pfn1:altsyncram1"
Info: Elaborating entity "cpu_0_register_bank_a_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_4be1.tdf
    Info: Found entity 1: altsyncram_4be1
Info: Elaborating entity "altsyncram_4be1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_4be1:auto_generated"
Info: Elaborating entity "cpu_0_register_bank_b_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_5be1.tdf
    Info: Found entity 1: altsyncram_5be1
Info: Elaborating entity "altsyncram_5be1" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_5be1:auto_generated"
Info: Elaborating entity "cpu_0_dc_tag_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_vf22.tdf
    Info: Found entity 1: altsyncram_vf22
Info: Elaborating entity "altsyncram_vf22" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_vf22:auto_generated"
Info: Elaborating entity "cpu_0_dc_data_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_a422.tdf
    Info: Found entity 1: altsyncram_a422
Info: Elaborating entity "altsyncram_a422" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated"
Info: Elaborating entity "cpu_0_mult_cell" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/altmult_add.tdf
    Info: Found entity 1: altmult_add
Info: Elaborating entity "altmult_add" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_4cr2.tdf
    Info: Found entity 1: mult_add_4cr2
Info: Elaborating entity "mult_add_4cr2" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/ded_mult_2o81.tdf
    Info: Found entity 1: ded_mult_2o81
Info: Elaborating entity "ded_mult_2o81" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_93c.tdf
    Info: Found entity 1: dffpipe_93c
Info: Elaborating entity "dffpipe_93c" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result"
Info: Elaborating entity "altmult_add" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_6cr2.tdf
    Info: Found entity 1: mult_add_6cr2
Info: Elaborating entity "mult_add_6cr2" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated"
Info: Elaborating entity "cpu_0_nios2_oci" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci"
Info: Elaborating entity "cpu_0_nios2_oci_debug" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug"
Info: Elaborating entity "cpu_0_nios2_ocimem" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem"
Info: Elaborating entity "cpu_0_ociram_lpm_dram_bdp_component_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_c572.tdf
    Info: Found entity 1: altsyncram_c572
Info: Elaborating entity "altsyncram_c572" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated"
Info: Elaborating entity "cpu_0_nios2_avalon_reg" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg"
Info: Elaborating entity "cpu_0_nios2_oci_break" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break"
Info: Elaborating entity "cpu_0_nios2_oci_xbrk" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk"
Info: Elaborating entity "cpu_0_nios2_oci_dbrk" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk"
Info: Elaborating entity "cpu_0_nios2_oci_match_paired" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_paired:cpu_0_nios2_oci_dbrk_hit0_match_paired"
Info: Elaborating entity "cpu_0_nios2_oci_match_single" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit0_match_single"
Info: Elaborating entity "cpu_0_nios2_oci_itrace" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace"
Info: Elaborating entity "cpu_0_nios2_oci_dtrace" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace"
Info: Elaborating entity "cpu_0_nios2_oci_td_mode" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace|cpu_0_nios2_oci_td_mode:cpu_0_nios2_oci_trc_ctrl_td_mode"
Info: Elaborating entity "cpu_0_nios2_oci_fifo" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo"
Info: Elaborating entity "cpu_0_nios2_oci_compute_tm_count" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_compute_tm_count:cpu_0_nios2_oci_compute_tm_count_tm_count"
Info: Elaborating entity "cpu_0_nios2_oci_fifowp_inc" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifowp_inc:cpu_0_nios2_oci_fifowp_inc_fifowp"
Info: Elaborating entity "cpu_0_nios2_oci_fifocount_inc" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifocount_inc:cpu_0_nios2_oci_fifocount_inc_fifocount"
Info: Elaborating entity "cpu_0_nios2_oci_pib" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_pib:the_cpu_0_nios2_oci_pib"
Info: Elaborating entity "cpu_0_nios2_oci_im" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im"
Info: Elaborating entity "cpu_0_traceram_lpm_dram_bdp_component_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component"
Info: Elaborating entity "altsyncram" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Elaborated megafunction instantiation "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_e502.tdf
    Info: Found entity 1: altsyncram_e502
Info: Elaborating entity "altsyncram_e502" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated"
Info: Elaborating entity "cpu_0_jtag_debug_module_wrapper" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper"
Info: Elaborating entity "cpu_0_jtag_debug_module" for hierarchy "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1"
Info: Elaborating entity "jtag_uart_0_avalon_jtag_slave_arbitrator" for hierarchy "system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave"
Info: Elaborating entity "jtag_uart_0" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0"
Info: Elaborating entity "jtag_uart_0_scfifo_w" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/scfifo.tdf
    Info: Found entity 1: scfifo
Info: Elaborating entity "scfifo" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo"
Info: Elaborated megafunction instantiation "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo"
Info: Found 1 design units, including 1 entities, in source file db/scfifo_1n21.tdf
    Info: Found entity 1: scfifo_1n21
Info: Elaborating entity "scfifo_1n21" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_8t21.tdf
    Info: Found entity 1: a_dpfifo_8t21
Info: Elaborating entity "a_dpfifo_8t21" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo"
Info: Found 1 design units, including 1 entities, in source file db/a_fefifo_7cf.tdf
    Info: Found entity 1: a_fefifo_7cf
Info: Elaborating entity "a_fefifo_7cf" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state"
Info: Found 1 design units, including 1 entities, in source file db/cntr_rj7.tdf
    Info: Found entity 1: cntr_rj7
Info: Elaborating entity "cntr_rj7" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw"
Info: Found 1 design units, including 1 entities, in source file db/dpram_5h21.tdf
    Info: Found entity 1: dpram_5h21
Info: Elaborating entity "dpram_5h21" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_9tl1.tdf
    Info: Found entity 1: altsyncram_9tl1
Info: Elaborating entity "altsyncram_9tl1" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2"
Info: Found 1 design units, including 1 entities, in source file db/cntr_dl8.tdf
    Info: Found entity 1: cntr_dl8
Info: Elaborating entity "cntr_dl8" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_dl8:rd_ptr_count"
Info: Elaborating entity "jtag_uart_0_scfifo_r" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v
    Info: Found entity 1: alt_jtag_atlantic
Info: Elaborating entity "alt_jtag_atlantic" for hierarchy "system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic"
Info: Elaborated megafunction instantiation "system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic"
Info: Elaborating entity "sdram_0_s1_arbitrator" for hierarchy "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1"
Info: Elaborating entity "rdv_fifo_for_clock_0_out_to_sdram_0_s1_module" for hierarchy "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1"
Info: Elaborating entity "rdv_fifo_for_clock_1_out_to_sdram_0_s1_module" for hierarchy "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1"
Info: Elaborating entity "sdram_0" for hierarchy "system_0:u0|sdram_0:the_sdram_0"
Warning (10005): Verilog HDL or VHDL warning at sdram_0.v(352): ignoring full_case attribute on case statement with explicit default
Info: Elaborating entity "sdram_0_input_efifo_module" for hierarchy "system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module"
Warning (10005): Verilog HDL or VHDL warning at sdram_0.v(67): ignoring full_case attribute on case statement with explicit default
Warning (10005): Verilog HDL or VHDL warning at sdram_0.v(93): ignoring full_case attribute on case statement with explicit default
Warning (10005): Verilog HDL or VHDL warning at sdram_0.v(129): ignoring full_case attribute on case statement with explicit default
Info: Elaborating entity "sram_0_avalon_slave_0_arbitrator" for hierarchy "system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0"
Info: Elaborating entity "sram_0" for hierarchy "system_0:u0|sram_0:the_sram_0"
Info: Elaborating entity "SRAM_16Bit_512K" for hierarchy "system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K"
Info: Elaborating entity "timer_0_s1_arbitrator" for hierarchy "system_0:u0|timer_0_s1_arbitrator:the_timer_0_s1"
Info: Elaborating entity "timer_0" for hierarchy "system_0:u0|timer_0:the_timer_0"
Info: Elaborating entity "timer_1_s1_arbitrator" for hierarchy "system_0:u0|timer_1_s1_arbitrator:the_timer_1_s1"
Info: Elaborating entity "timer_1" for hierarchy "system_0:u0|timer_1:the_timer_1"
Info: Elaborating entity "tri_state_bridge_0_avalon_slave_arbitrator" for hierarchy "system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave"
Info: Elaborating entity "system_0_reset_clk_domain_synch_module" for hierarchy "system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch"
Info: Elaborating entity "system_0_reset_clk_50_domain_synch_module" for hierarchy "system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch"
Info: Elaborating entity "I2C_AV_Config" for hierarchy "I2C_AV_Config:u1"
Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(55): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(106): truncated value with size 32 to match size of target (6)
Info: Elaborating entity "I2C_Controller" for hierarchy "I2C_AV_Config:u1|I2C_Controller:u0"
Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(90): truncated value with size 32 to match size of target (6)
Warning: Port "address_b" on the entity instantiation of "cpu_0_traceram_lpm_dram_bdp_component" is connected to a signal of width 17. The formal width of the signal in the module is 7.  Extra bits will be driven by GND.
Warning: Port "jdo" on the entity instantiation of "the_cpu_0_nios2_oci_itrace" is connected to a signal of width 38. The formal width of the signal in the module is 16.  Extra bits will be driven by GND.
Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit3_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit2_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "dbrka" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit2_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "dbrkb" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit2_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit1_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "dbrk" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit0_match_single" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "dbrka" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit0_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "dbrkb" on the entity instantiation of "cpu_0_nios2_oci_dbrk_hit0_match_paired" is connected to a signal of width 78. The formal width of the signal in the module is 71.  Extra bits will be driven by GND.
Warning: Port "oci_ienable" on the entity instantiation of "the_cpu_0_nios2_oci" is connected to a signal of width 6. The formal width of the signal in the module is 32.  Extra bits will be left dangling without any fanout logic.
Info: Found 6 design units, including 2 entities, in source file ../../../altera/quartus60/libraries/megafunctions/sld_hub.vhd
    Info: Found design unit 1: HUB_PACK
    Info: Found design unit 2: JTAG_PACK
    Info: Found design unit 3: sld_hub-rtl
    Info: Found design unit 4: sld_jtag_state_machine-rtl
    Info: Found entity 1: sld_hub
    Info: Found entity 2: sld_jtag_state_machine
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst"
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/lpm_shiftreg.tdf
    Info: Found entity 1: lpm_shiftreg
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/lpm_decode.tdf
    Info: Found entity 1: lpm_decode
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|lpm_decode:instruction_decoder", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Found 1 design units, including 1 entities, in source file db/decode_aoi.tdf
    Info: Found entity 1: decode_aoi
Info: Found 2 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd
    Info: Found design unit 1: sld_dffex-DFFEX
    Info: Found entity 1: sld_dffex
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:RESET", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:IRSR", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_dffex:IRF_ENA", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Found 2 design units, including 1 entities, in source file ../../../altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd
    Info: Found design unit 1: sld_rom_sr-INFO_REG
    Info: Found entity 1: sld_rom_sr
Info: Elaborated megafunction instantiation "sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG", which is child of megafunction instantiation "sld_hub:sld_hub_inst"
Info: Instantiated megafunction "sld_hub:sld_hub_inst" with the following parameter:
    Info: Parameter "SLD_HUB_IP_VERSION" = "1"
    Info: Parameter "SLD_HUB_IP_MINOR_VERSION" = "3"
    Info: Parameter "SLD_COMMON_IP_VERSION" = "0"
    Info: Parameter "N_NODES" = "2"
    Info: Parameter "N_SEL_BITS" = "2"
    Info: Parameter "N_NODE_IR_BITS" = "5"
    Info: Parameter "NODE_INFO" = "0000110000000000011011100000000000010001000100000100011000000000"
    Info: Parameter "COMPILATION_MODE" = "0"
    Info: Parameter "DEVICE_FAMILY" = "Cyclone II"
Info: Power-up level of register "system_0:u0|sdram_0:the_sdram_0|i_addr[5]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|sdram_0:the_sdram_0|i_addr[5]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|sdram_0:the_sdram_0|i_addr[4]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|sdram_0:the_sdram_0|i_addr[4]" with stuck data_in port to stuck value VCC
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[31]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[30]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[29]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[28]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[27]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[26]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[25]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[24]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[22]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[21]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[20]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[19]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[18]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ipending_reg[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|tracemem_tw" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|trc_im_addr[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_break_pulse" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_goto0" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_goto1" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|xbrk_hit1" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|xbrk_hit2" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|xbrk_hit3" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|E_xbrk_goto0" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|E_xbrk_goto1" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|dbrk_hit0_latch" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|dbrk_hit1_latch" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|dbrk_hit2_latch" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|dbrk_hit3_latch" with stuck data_in port to stuck value GND
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[31]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[31]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[30]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[30]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[29]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[29]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[28]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[28]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[27]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[27]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[26]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[26]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[25]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[25]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[24]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[24]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[23]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[23]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[22]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[22]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[21]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[21]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[20]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[20]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[19]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[19]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[18]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[18]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[17]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[17]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[16]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[16]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[15]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[15]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[14]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[14]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[13]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[13]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[12]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[12]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[11]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[11]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[10]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[10]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[9]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[9]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[8]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[8]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[7]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[7]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[6]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[6]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[2]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[2]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[0]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg|oci_ienable[0]" with stuck data_in port to stuck value VCC
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|xbrk_break" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|M_xbrk_goto0" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk|M_xbrk_goto1" with stuck data_in port to stuck value GND
Warning: No clock transition on "system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_write_request" register due to stuck clock or clock enable
Warning: Reduced register "system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_write_request" with stuck clock_enable port to stuck value GND
Warning: Synthesized away the following node(s):
    Warning: Synthesized away the following RAM node(s):
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[0]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[1]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[2]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[3]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[4]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[5]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[6]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[7]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[8]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[9]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[10]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[11]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[12]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[13]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[14]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[15]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[16]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[17]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[18]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[19]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[20]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[21]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[22]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[23]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[24]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[25]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[26]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[27]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[28]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[29]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[30]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[31]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[32]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[33]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[34]"
        Warning: Synthesized away node "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated|q_a[35]"
    Warning: Synthesized away the following PLL node(s):
        Warning: Synthesized away node "Audio_PLL:PLL2|altpll:altpll_component|_clk0"
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[19]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|mI2C_DATA[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[19]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "I2C_AV_Config:u1|I2C_Controller:u0|SD[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ienable_reg[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|A_ienable_reg[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|E_control_rd_data_without_mmu_regs[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|M_control_rd_data[2]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_tri_state_bridge_0_avalon_slave_end_xfer" merged to single register "system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|d1_sram_0_avalon_slave_0_end_xfer" merged to single register "system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|d1_reasons_to_wait", power-up level changed
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[10]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[9]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[8]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[7]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[6]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[3]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[2]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[1]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|sdram_0:the_sdram_0|i_addr[0]" merged to single register "system_0:u0|sdram_0:the_sdram_0|i_addr[11]"
    Info: Duplicate register "system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|d1_cpu_0_jtag_debug_module_end_xfer" merged to single register "system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|d1_reasons_to_wait", power-up level changed
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|trigger_state" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|full_6" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|full_6"
    Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|full_5" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|full_5"
    Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|full_4" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|full_4"
    Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|full_3" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|full_3"
    Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|full_2" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|full_2"
    Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|full_1" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|full_1"
    Info: Duplicate register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1|full_0" merged to single register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1|full_0"
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|dbrk_break" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_slavearbiterlockenable" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|sdram_0_s1_arb_share_counter" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break|trigbrktype" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "I2C_AV_Config:u1|mI2C_DATA[21]" merged to single register "I2C_AV_Config:u1|mI2C_DATA[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u1|mI2C_DATA[20]" merged to single register "I2C_AV_Config:u1|mI2C_DATA[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u1|mI2C_DATA[18]" merged to single register "I2C_AV_Config:u1|mI2C_DATA[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u1|I2C_Controller:u0|SD[21]" merged to single register "I2C_AV_Config:u1|I2C_Controller:u0|SD[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u1|I2C_Controller:u0|SD[20]" merged to single register "I2C_AV_Config:u1|I2C_Controller:u0|SD[22]", power-up level changed
    Info: Duplicate register "I2C_AV_Config:u1|I2C_Controller:u0|SD[18]" merged to single register "I2C_AV_Config:u1|I2C_Controller:u0|SD[22]", power-up level changed
    Info: Duplicate register "system_0:u0|cpu_0:the_cpu_0|D_ctrl_jmp_direct" merged to single register "system_0:u0|cpu_0:the_cpu_0|D_ctrl_a_not_src"
    Info: Duplicate register "system_0:u0|cpu_0:the_cpu_0|D_ctrl_b_is_dst" merged to single register "system_0:u0|cpu_0:the_cpu_0|D_ctrl_b_not_src"
Warning: Reduced register "system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_share_counter[2]" with stuck data_in port to stuck value GND
Info: State machine "|DE2_NIOS_DEVICE_LED|I2C_AV_Config:u1|mSetup_ST" contains 3 states
Info: State machine "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_state" contains 6 states
Info: State machine "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_next" contains 4 states
Info: State machine "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_state" contains 9 states
Info: State machine "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_next" contains 4 states
Info: State machine "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state" contains 3 states
Info: State machine "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state" contains 3 states
Info: State machine "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state" contains 3 states
Info: State machine "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_DEVICE_LED|I2C_AV_Config:u1|mSetup_ST"
Info: Encoding result for state machine "|DE2_NIOS_DEVICE_LED|I2C_AV_Config:u1|mSetup_ST"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "I2C_AV_Config:u1|mSetup_ST.0000"
        Info: Encoded state bit "I2C_AV_Config:u1|mSetup_ST.0010"
        Info: Encoded state bit "I2C_AV_Config:u1|mSetup_ST.0001"
    Info: State "|DE2_NIOS_DEVICE_LED|I2C_AV_Config:u1|mSetup_ST.0000" uses code string "000"
    Info: State "|DE2_NIOS_DEVICE_LED|I2C_AV_Config:u1|mSetup_ST.0001" uses code string "101"
    Info: State "|DE2_NIOS_DEVICE_LED|I2C_AV_Config:u1|mSetup_ST.0010" uses code string "110"
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_state"
Info: Encoding result for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_state"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.101"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.111"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.001"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.011"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.010"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_state.000"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_state.000" uses code string "000000"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_state.010" uses code string "000011"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_state.011" uses code string "000101"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_state.001" uses code string "001001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_state.111" uses code string "010001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_state.101" uses code string "100001"
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_next"
Info: Encoding result for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_next"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_next.101"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_next.010"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_next.111"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|i_next.000"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_next.000" uses code string "0000"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_next.111" uses code string "0011"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_next.010" uses code string "0101"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|i_next.101" uses code string "1001"
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_state"
Info: Encoding result for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_state"
    Info: Completed encoding using 9 state bits
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.100000000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.010000000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.001000000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000100000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000010000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000001000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000000100"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000000010"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_state.000000001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_state.000000001" uses code string "000000000"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_state.000100000" uses code string "000100001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_state.000010000" uses code string "000010001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_state.000001000" uses code string "000001001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_state.100000000" uses code string "100000001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_state.000000100" uses code string "000000101"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_state.000000010" uses code string "000000011"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_state.001000000" uses code string "001000001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_state.010000000" uses code string "010000001"
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_next"
Info: Encoding result for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_next"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_next.010000000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_next.000010000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_next.000001000"
        Info: Encoded state bit "system_0:u0|sdram_0:the_sdram_0|m_next.000000001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_next.000000001" uses code string "0000"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_next.000001000" uses code string "0011"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_next.010000000" uses code string "1001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|sdram_0:the_sdram_0|m_next.000010000" uses code string "0101"
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state"
Info: Encoding result for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.100"
        Info: Encoded state bit "system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.010"
        Info: Encoded state bit "system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.001" uses code string "000"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.100" uses code string "101"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM|master_state.010" uses code string "011"
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state"
Info: Encoding result for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.100"
        Info: Encoded state bit "system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.010"
        Info: Encoded state bit "system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.001" uses code string "000"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.010" uses code string "011"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM|slave_state.100" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state"
Info: Encoding result for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.100"
        Info: Encoded state bit "system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.010"
        Info: Encoded state bit "system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.001" uses code string "000"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.100" uses code string "101"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM|master_state.010" uses code string "011"
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state"
Info: Encoding result for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.100"
        Info: Encoded state bit "system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.010"
        Info: Encoded state bit "system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.001" uses code string "000"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.010" uses code string "011"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.100" uses code string "101"
Warning: Reduced register "system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM|slave_state.100" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_slavearbiterlockenable" with stuck data_in port to stuck value GND
Info: Inferred 1 megafunctions from design logic
    Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=64, WIDTH_A=16) from the following design logic: "I2C_AV_Config:u1|Ram0~37"
Info: State machine "|DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize" contains 6 states
Info: Selected Auto state machine encoding method for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize"
Info: Encoding result for state machine "|DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.011"
        Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.100"
        Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.101"
        Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.010"
        Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.001"
        Info: Encoded state bit "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.000"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.000" uses code string "000000"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.001" uses code string "000011"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.010" uses code string "000101"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.101" uses code string "001001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.100" uses code string "010001"
    Info: State "|DE2_NIOS_DEVICE_LED|system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.011" uses code string "100001"
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.001" with stuck data_in port to stuck value GND
Warning: Reduced register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|DRsize.011" with stuck data_in port to stuck value GND
Info: Elaborated megafunction instantiation "I2C_AV_Config:u1|altsyncram:Ram0_rtl_0"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_mj01.tdf
    Info: Found entity 1: altsyncram_mj01
Warning: The bidir "OTG_DATA[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[8]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[9]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[10]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[11]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[12]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[13]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[14]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "OTG_DATA[15]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "LCD_DATA[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SD_CMD" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[8]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[9]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[10]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[11]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[12]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[13]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[14]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "ENET_DATA[15]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "AUD_BCLK" has no source; inserted an always disabled tri-state buffer.
Warning: Replaced VCC or GND feeding tri-state bus SD_DAT3~0 with an always-enabled tri-state buffer
Warning: The bidir "AUD_DACLRCK" has no source; inserted an always disabled tri-state buffer.
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Converted presettable and clearable register to equivalent circuits with latches. Registers will power-up to an undefined state, and DEVCLRn will place the registers in an undefined state.
    Info: Register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir" converted into equivalent circuit using register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir~$emulated" and latch "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir~7"
    Info: Register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr" converted into equivalent circuit using register "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr~$emulated" and latch "system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr~8"
Info: Duplicate registers merged to single register
    Info: Duplicate register "system_0:u0|cpu_0:the_cpu_0|reset_d1" merged to single register "system_0:u0|clock_0:the_clock_0|slave_byteenable_d1[1]", power-up level changed
Warning: Reduced register "system_0:u0|sdram_0:the_sdram_0|m_count[2]" with stuck data_in port to stuck value GND
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "SD_DAT3~1"
    Warning: Node "AUD_ADCLRCK~2"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "HEX0[0]" stuck at GND
    Warning: Pin "HEX0[1]" stuck at GND
    Warning: Pin "HEX0[2]" stuck at GND
    Warning: Pin "HEX0[3]" stuck at GND
    Warning: Pin "HEX0[4]" stuck at GND
    Warning: Pin "HEX0[5]" stuck at GND
    Warning: Pin "HEX0[6]" stuck at GND
    Warning: Pin "HEX1[0]" stuck at GND
    Warning: Pin "HEX1[1]" stuck at GND
    Warning: Pin "HEX1[2]" stuck at GND
    Warning: Pin "HEX1[3]" stuck at GND
    Warning: Pin "HEX1[4]" stuck at GND
    Warning: Pin "HEX1[5]" stuck at GND
    Warning: Pin "HEX1[6]" stuck at GND
    Warning: Pin "HEX2[0]" stuck at GND
    Warning: Pin "HEX2[1]" stuck at GND
    Warning: Pin "HEX2[2]" stuck at GND
    Warning: Pin "HEX2[3]" stuck at GND
    Warning: Pin "HEX2[4]" stuck at GND
    Warning: Pin "HEX2[5]" stuck at GND
    Warning: Pin "HEX2[6]" stuck at GND
    Warning: Pin "HEX3[0]" stuck at GND
    Warning: Pin "HEX3[1]" stuck at GND
    Warning: Pin "HEX3[2]" stuck at GND
    Warning: Pin "HEX3[3]" stuck at GND
    Warning: Pin "HEX3[4]" stuck at GND
    Warning: Pin "HEX3[5]" stuck at GND
    Warning: Pin "HEX3[6]" stuck at GND
    Warning: Pin "HEX4[0]" stuck at GND
    Warning: Pin "HEX4[1]" stuck at GND
    Warning: Pin "HEX4[2]" stuck at GND
    Warning: Pin "HEX4[3]" stuck at GND
    Warning: Pin "HEX4[4]" stuck at GND
    Warning: Pin "HEX4[5]" stuck at GND
    Warning: Pin "HEX4[6]" stuck at GND
    Warning: Pin "HEX5[0]" stuck at GND
    Warning: Pin "HEX5[1]" stuck at GND
    Warning: Pin "HEX5[2]" stuck at GND
    Warning: Pin "HEX5[3]" stuck at GND
    Warning: Pin "HEX5[4]" stuck at GND
    Warning: Pin "HEX5[5]" stuck at GND
    Warning: Pin "HEX5[6]" stuck at GND
    Warning: Pin "HEX6[0]" stuck at GND
    Warning: Pin "HEX6[1]" stuck at GND
    Warning: Pin "HEX6[2]" stuck at GND
    Warning: Pin "HEX6[3]" stuck at GND
    Warning: Pin "HEX6[4]" stuck at GND
    Warning: Pin "HEX6[5]" stuck at GND
    Warning: Pin "HEX6[6]" stuck at GND
    Warning: Pin "HEX7[0]" stuck at GND
    Warning: Pin "HEX7[1]" stuck at GND
    Warning: Pin "HEX7[2]" stuck at GND
    Warning: Pin "HEX7[3]" stuck at GND
    Warning: Pin "HEX7[4]" stuck at GND
    Warning: Pin "HEX7[5]" stuck at GND
    Warning: Pin "HEX7[6]" stuck at GND
    Warning: Pin "LEDG[0]" stuck at GND
    Warning: Pin "LEDG[1]" stuck at GND
    Warning: Pin "LEDG[2]" stuck at GND
    Warning: Pin "LEDG[3]" stuck at GND
    Warning: Pin "LEDG[4]" stuck at GND
    Warning: Pin "LEDG[5]" stuck at GND
    Warning: Pin "LEDG[6]" stuck at GND
    Warning: Pin "LEDG[7]" stuck at GND
    Warning: Pin "LEDG[8]" stuck at GND
    Warning: Pin "LEDR[0]" stuck at GND
    Warning: Pin "LEDR[1]" stuck at GND
    Warning: Pin "LEDR[2]" stuck at GND
    Warning: Pin "LEDR[3]" stuck at GND
    Warning: Pin "LEDR[4]" stuck at GND
    Warning: Pin "LEDR[5]" stuck at GND
    Warning: Pin "LEDR[6]" stuck at GND
    Warning: Pin "LEDR[7]" stuck at GND
    Warning: Pin "LEDR[8]" stuck at GND
    Warning: Pin "LEDR[9]" stuck at GND
    Warning: Pin "LEDR[10]" stuck at GND
    Warning: Pin "LEDR[11]" stuck at GND
    Warning: Pin "LEDR[12]" stuck at GND
    Warning: Pin "LEDR[13]" stuck at GND
    Warning: Pin "LEDR[14]" stuck at GND
    Warning: Pin "LEDR[15]" stuck at GND
    Warning: Pin "LEDR[16]" stuck at GND
    Warning: Pin "LEDR[17]" stuck at GND
    Warning: Pin "UART_TXD" stuck at GND
    Warning: Pin "IRDA_TXD" stuck at GND
    Warning: Pin "DRAM_CKE" stuck at VCC
    Warning: Pin "FL_RST_N" stuck at VCC
    Warning: Pin "OTG_ADDR[0]" stuck at GND
    Warning: Pin "OTG_ADDR[1]" stuck at GND
    Warning: Pin "OTG_CS_N" stuck at GND
    Warning: Pin "OTG_RD_N" stuck at GND
    Warning: Pin "OTG_WR_N" stuck at GND
    Warning: Pin "OTG_RST_N" stuck at GND
    Warning: Pin "OTG_DACK0_N" stuck at GND
    Warning: Pin "OTG_DACK1_N" stuck at GND
    Warning: Pin "LCD_ON" stuck at VCC
    Warning: Pin "LCD_BLON" stuck at VCC
    Warning: Pin "LCD_RW" stuck at GND
    Warning: Pin "LCD_EN" stuck at GND
    Warning: Pin "LCD_RS" stuck at GND
    Warning: Pin "SD_CLK" stuck at GND
    Warning: Pin "TDO" stuck at GND
    Warning: Pin "VGA_CLK" stuck at GND
    Warning: Pin "VGA_HS" stuck at GND
    Warning: Pin "VGA_VS" stuck at GND
    Warning: Pin "VGA_BLANK" stuck at GND
    Warning: Pin "VGA_SYNC" stuck at GND
    Warning: Pin "VGA_R[0]" stuck at GND
    Warning: Pin "VGA_R[1]" stuck at GND
    Warning: Pin "VGA_R[2]" stuck at GND
    Warning: Pin "VGA_R[3]" stuck at GND
    Warning: Pin "VGA_R[4]" stuck at GND
    Warning: Pin "VGA_R[5]" stuck at GND
    Warning: Pin "VGA_R[6]" stuck at GND
    Warning: Pin "VGA_R[7]" stuck at GND
    Warning: Pin "VGA_R[8]" stuck at GND
    Warning: Pin "VGA_R[9]" stuck at GND
    Warning: Pin "VGA_G[0]" stuck at GND
    Warning: Pin "VGA_G[1]" stuck at GND
    Warning: Pin "VGA_G[2]" stuck at GND
    Warning: Pin "VGA_G[3]" stuck at GND
    Warning: Pin "VGA_G[4]" stuck at GND
    Warning: Pin "VGA_G[5]" stuck at GND
    Warning: Pin "VGA_G[6]" stuck at GND
    Warning: Pin "VGA_G[7]" stuck at GND
    Warning: Pin "VGA_G[8]" stuck at GND
    Warning: Pin "VGA_G[9]" stuck at GND
    Warning: Pin "VGA_B[0]" stuck at GND
    Warning: Pin "VGA_B[1]" stuck at GND
    Warning: Pin "VGA_B[2]" stuck at GND
    Warning: Pin "VGA_B[3]" stuck at GND
    Warning: Pin "VGA_B[4]" stuck at GND
    Warning: Pin "VGA_B[5]" stuck at GND
    Warning: Pin "VGA_B[6]" stuck at GND
    Warning: Pin "VGA_B[7]" stuck at GND
    Warning: Pin "VGA_B[8]" stuck at GND
    Warning: Pin "VGA_B[9]" stuck at GND
    Warning: Pin "ENET_CMD" stuck at GND
    Warning: Pin "ENET_CS_N" stuck at GND
    Warning: Pin "ENET_WR_N" stuck at GND
    Warning: Pin "ENET_RD_N" stuck at GND
    Warning: Pin "ENET_RST_N" stuck at GND
    Warning: Pin "ENET_CLK" stuck at GND
    Warning: Pin "AUD_DACDAT" stuck at GND
    Warning: Pin "AUD_XCK" stuck at GND
    Warning: Pin "TD_RESET" stuck at VCC
Warning: Design contains 43 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "CLOCK_27"
    Warning: No output dependent on input pin "EXT_CLOCK"
    Warning: No output dependent on input pin "SW[0]"
    Warning: No output dependent on input pin "SW[1]"
    Warning: No output dependent on input pin "SW[2]"
    Warning: No output dependent on input pin "SW[3]"
    Warning: No output dependent on input pin "SW[4]"
    Warning: No output dependent on input pin "SW[5]"
    Warning: No output dependent on input pin "SW[6]"
    Warning: No output dependent on input pin "SW[7]"
    Warning: No output dependent on input pin "SW[8]"
    Warning: No output dependent on input pin "SW[9]"
    Warning: No output dependent on input pin "SW[10]"
    Warning: No output dependent on input pin "SW[11]"
    Warning: No output dependent on input pin "SW[12]"
    Warning: No output dependent on input pin "SW[13]"
    Warning: No output dependent on input pin "SW[14]"
    Warning: No output dependent on input pin "SW[15]"
    Warning: No output dependent on input pin "SW[16]"
    Warning: No output dependent on input pin "SW[17]"
    Warning: No output dependent on input pin "UART_RXD"
    Warning: No output dependent on input pin "IRDA_RXD"
    Warning: No output dependent on input pin "OTG_INT0"
    Warning: No output dependent on input pin "OTG_INT1"
    Warning: No output dependent on input pin "OTG_DREQ0"
    Warning: No output dependent on input pin "OTG_DREQ1"
    Warning: No output dependent on input pin "TDI"
    Warning: No output dependent on input pin "TCK"
    Warning: No output dependent on input pin "TCS"
    Warning: No output dependent on input pin "PS2_DAT"
    Warning: No output dependent on input pin "PS2_CLK"
    Warning: No output dependent on input pin "ENET_INT"
    Warning: No output dependent on input pin "AUD_ADCDAT"
    Warning: No output dependent on input pin "TD_DATA[0]"
    Warning: No output dependent on input pin "TD_DATA[1]"
    Warning: No output dependent on input pin "TD_DATA[2]"
    Warning: No output dependent on input pin "TD_DATA[3]"
    Warning: No output dependent on input pin "TD_DATA[4]"
    Warning: No output dependent on input pin "TD_DATA[5]"
    Warning: No output dependent on input pin "TD_DATA[6]"
    Warning: No output dependent on input pin "TD_DATA[7]"
    Warning: No output dependent on input pin "TD_HS"
    Warning: No output dependent on input pin "TD_VS"
Info: Implemented 5580 device resources after synthesis - the final resource count might be different
    Info: Implemented 51 input pins
    Info: Implemented 219 output pins
    Info: Implemented 159 bidirectional pins
    Info: Implemented 4916 logic cells
    Info: Implemented 229 RAM segments
    Info: Implemented 1 ClockLock PLLs
    Info: Implemented 4 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 547 warnings
    Info: Processing ended: Sun Apr 08 00:52:27 2007
    Info: Elapsed time: 00:01:34


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.map.smsg.


