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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 8.985 ns
From           : SRAM_DQ[5]
To             : system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[21]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.302 ns
From           : I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1]
To             : I2C_SCLK
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 8.809 ns
From           : AUD_DACLRCK
To             : AUD_ADCLRCK
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.643 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'SDRAM_PLL:PLL1|altpll:altpll_component|_clk1'
Slack          : 0.526 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 105.55 MHz ( period = 9.474 ns )
From           : system_0:u0|cpu_0:the_cpu_0|d_address[23]
To             : system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6]
From Clock     : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
To Clock       : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK_50'
Slack          : 10.831 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 109.06 MHz ( period = 9.169 ns )
From           : system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address
To             : system_0:u0|sdram_0:the_sdram_0|m_addr[5]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 139.55 MHz ( period = 7.166 ns )
From           : sld_hub:sld_hub_inst|jtag_debug_mode_usr1
To             : system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[11]
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'SDRAM_PLL:PLL1|altpll:altpll_component|_clk1'
Slack          : 0.391 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty
To             : system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty
From Clock     : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
To Clock       : SDRAM_PLL:PLL1|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Clock Hold: 'CLOCK_50'
Slack          : 0.391 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : system_0:u0|sdram_0:the_sdram_0|i_cmd[3]
To             : system_0:u0|sdram_0:the_sdram_0|i_cmd[3]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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