Version 6.0 Build 178 04/27/2006 SJ Web Edition
11
767
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
Reset_Delay
# storage
db|DE2_NIOS_DEVICE_LED.(1).cnf
db|DE2_NIOS_DEVICE_LED.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Reset_Delay.v
b7b988df2e64acc7ee3c985f65b56f76
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
Reset_Delay:delay1
}
# end
# entity
SDRAM_PLL
# storage
db|DE2_NIOS_DEVICE_LED.(2).cnf
db|DE2_NIOS_DEVICE_LED.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SDRAM_PLL.v
44387b781dfb8ec9b8ffa0f2191
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
SDRAM_PLL:PLL1
}
# end
# entity
altpll
# storage
db|DE2_NIOS_DEVICE_LED.(3).cnf
db|DE2_NIOS_DEVICE_LED.(3).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altpll.tdf
eda762e5901c3e66939b23e413541e
6
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
FAST
PARAMETER_UNKNOWN
USR
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
20000
PARAMETER_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_DEC
USR
CLK1_MULTIPLY_BY
2
PARAMETER_DEC
USR
CLK0_MULTIPLY_BY
1
PARAMETER_DEC
USR
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
2
PARAMETER_DEC
USR
CLK1_DIVIDE_BY
1
PARAMETER_DEC
USR
CLK0_DIVIDE_BY
1
PARAMETER_DEC
USR
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK0_PHASE_SHIFT
-3000
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_DEC
USR
CLK1_DUTY_CYCLE
50
PARAMETER_DEC
USR
CLK0_DUTY_CYCLE
50
PARAMETER_DEC
USR
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
clkswitch
-1
1
areset
-1
1
pllena
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|stratix_pll.inc
5f8211898149ceae8264a0ea5036254f
..|..|..|altera|quartus60|libraries|megafunctions|stratixii_pll.inc
6d1985e16ab5f59a1fd6b0ae20978a4e
..|..|..|altera|quartus60|libraries|megafunctions|cycloneii_pll.inc
39a0d9d1237d1db39c848c3f9faffc
}
# hierarchies {
SDRAM_PLL:PLL1|altpll:altpll_component
}
# end
# entity
Audio_PLL
# storage
db|DE2_NIOS_DEVICE_LED.(4).cnf
db|DE2_NIOS_DEVICE_LED.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Audio_PLL.v
9f3fe96f98fa691b01af0a4c5ff919
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
Audio_PLL:PLL2
}
# end
# entity
altpll
# storage
db|DE2_NIOS_DEVICE_LED.(5).cnf
db|DE2_NIOS_DEVICE_LED.(5).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altpll.tdf
eda762e5901c3e66939b23e413541e
6
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
FAST
PARAMETER_UNKNOWN
USR
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
37037
PARAMETER_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_MULTIPLY_BY
92
PARAMETER_DEC
USR
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_DIVIDE_BY
135
PARAMETER_DEC
USR
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK0_DUTY_CYCLE
50
PARAMETER_DEC
USR
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
areset
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
clkswitch
-1
1
pllena
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
clkena
-1
2
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|stratix_pll.inc
5f8211898149ceae8264a0ea5036254f
..|..|..|altera|quartus60|libraries|megafunctions|stratixii_pll.inc
6d1985e16ab5f59a1fd6b0ae20978a4e
..|..|..|altera|quartus60|libraries|megafunctions|cycloneii_pll.inc
39a0d9d1237d1db39c848c3f9faffc
}
# hierarchies {
Audio_PLL:PLL2|altpll:altpll_component
}
# end
# entity
Audio_0
# storage
db|DE2_NIOS_DEVICE_LED.(8).cnf
db|DE2_NIOS_DEVICE_LED.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Audio_0.v
1c882bd83e3be9c81e7aaa42eb598191
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
AUDIO_DAC_FIFO
# storage
db|DE2_NIOS_DEVICE_LED.(9).cnf
db|DE2_NIOS_DEVICE_LED.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
AUDIO_DAC_FIFO.v
77d2b1a1f83ac11dbbacf3348b6c256
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
REF_CLK
18432000
PARAMETER_DEC
USR
SAMPLE_RATE
48000
PARAMETER_DEC
USR
DATA_WIDTH
16
PARAMETER_DEC
USR
CHANNEL_NUM
2
PARAMETER_DEC
USR
}
# end
# entity
FIFO_16_256
# storage
db|DE2_NIOS_DEVICE_LED.(10).cnf
db|DE2_NIOS_DEVICE_LED.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
FIFO_16_256.v
1a6264e56144cfdd9243afa8477cfe
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
dcfifo
# storage
db|DE2_NIOS_DEVICE_LED.(11).cnf
db|DE2_NIOS_DEVICE_LED.(11).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|dcfifo.tdf
f52f61d654507d26e32b8ae857d410
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
16
PARAMETER_DEC
USR
LPM_NUMWORDS
256
PARAMETER_DEC
USR
LPM_WIDTHU
8
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
DEF
DELAY_RDUSEDW
1
PARAMETER_UNKNOWN
DEF
DELAY_WRUSEDW
1
PARAMETER_UNKNOWN
DEF
RDSYNC_DELAYPIPE
4
PARAMETER_DEC
USR
WRSYNC_DELAYPIPE
4
PARAMETER_DEC
USR
CLOCKS_ARE_SYNCHRONIZED
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
dcfifo_e6c1
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdreq
-1
3
rdclk
-1
3
q
-1
3
data
-1
3
aclr
-1
3
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|lpm_counter.inc
758886b0947dd67e65ec58adda9b948
..|..|..|altera|quartus60|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|a_fefifo.inc
c8498561e0bdc47f87b5548333d65f50
..|..|..|altera|quartus60|libraries|megafunctions|dffpipe.inc
8dfdb676c11c7bcef0694118a05ea2d
..|..|..|altera|quartus60|libraries|megafunctions|a_graycounter.inc
6bb463da5ec6451f39fdb64aba52ffc0
..|..|..|altera|quartus60|libraries|megafunctions|a_gray2bin.inc
2466d892d81838e113e13f4e76e71f2
..|..|..|altera|quartus60|libraries|megafunctions|alt_sync_fifo.inc
f4c68b9daca4a0e5389631895df30d0
..|..|..|altera|quartus60|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram_fifo.inc
12f7d8c61da985ee5330de43a169e
}
# end
# entity
dcfifo_e6c1
# storage
db|DE2_NIOS_DEVICE_LED.(12).cnf
db|DE2_NIOS_DEVICE_LED.(12).cnf
# case_insensitive
# source_file
db|dcfifo_e6c1.tdf
6edb4dfaaca44e1c4cb918567c97d818
6
# used_port {
wrreq
-1
3
wrfull
-1
3
wrclk
-1
3
rdreq
-1
3
rdclk
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
aclr
-1
3
}
# end
# entity
a_graycounter_g86
# storage
db|DE2_NIOS_DEVICE_LED.(13).cnf
db|DE2_NIOS_DEVICE_LED.(13).cnf
# case_insensitive
# source_file
db|a_graycounter_g86.tdf
1dd4dbd3336ec3a66a7329524c5ae142
6
# used_port {
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# end
# entity
a_graycounter_b17
# storage
db|DE2_NIOS_DEVICE_LED.(14).cnf
db|DE2_NIOS_DEVICE_LED.(14).cnf
# case_insensitive
# source_file
db|a_graycounter_b17.tdf
db787015846ada1068c013dccd995
6
# used_port {
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# end
# entity
a_graycounter_a17
# storage
db|DE2_NIOS_DEVICE_LED.(15).cnf
db|DE2_NIOS_DEVICE_LED.(15).cnf
# case_insensitive
# source_file
db|a_graycounter_a17.tdf
cf4e54b1306b181db561cd6595dacd4c
6
# used_port {
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# end
# entity
altsyncram_1731
# storage
db|DE2_NIOS_DEVICE_LED.(16).cnf
db|DE2_NIOS_DEVICE_LED.(16).cnf
# case_insensitive
# source_file
db|altsyncram_1731.tdf
5098bd7f2672e6fbe84f7d8e8e5eb93f
6
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
addressstall_b
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
aclr1
-1
3
}
# end
# entity
altsyncram_brg1
# storage
db|DE2_NIOS_DEVICE_LED.(17).cnf
db|DE2_NIOS_DEVICE_LED.(17).cnf
# case_insensitive
# source_file
db|altsyncram_brg1.tdf
e146ccb31e6143345a6eb0884ddf38
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b3
-1
3
data_b2
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
addressstall_a
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
aclr1
-1
3
wren_a
-1
1
data_a9
-1
2
data_a8
-1
2
data_a7
-1
2
data_a6
-1
2
data_a5
-1
2
data_a4
-1
2
data_a3
-1
2
data_a2
-1
2
data_a15
-1
2
data_a14
-1
2
data_a13
-1
2
data_a12
-1
2
data_a11
-1
2
data_a10
-1
2
data_a1
-1
2
data_a0
-1
2
}
# memory_file {
none
0
}
# end
# entity
alt_synch_pipe_nc8
# storage
db|DE2_NIOS_DEVICE_LED.(18).cnf
db|DE2_NIOS_DEVICE_LED.(18).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_nc8.tdf
ee2c19483a0f1b958153b2c38e5e0
6
# used_port {
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clrn
-1
3
clock
-1
3
}
# end
# entity
dffpipe_hd9
# storage
db|DE2_NIOS_DEVICE_LED.(19).cnf
db|DE2_NIOS_DEVICE_LED.(19).cnf
# case_insensitive
# source_file
db|dffpipe_hd9.tdf
7eaab988a6118ba908c4d28e8c12071
6
# used_port {
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clrn
-1
3
clock
-1
3
}
# end
# entity
alt_synch_pipe_hn7
# storage
db|DE2_NIOS_DEVICE_LED.(20).cnf
db|DE2_NIOS_DEVICE_LED.(20).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_hn7.tdf
6b18ab3efd55bee4894f3fbf1c9659bc
6
# used_port {
q0
-1
3
d0
-1
3
clrn
-1
3
clock
-1
3
}
# end
# entity
dffpipe_bo8
# storage
db|DE2_NIOS_DEVICE_LED.(21).cnf
db|DE2_NIOS_DEVICE_LED.(21).cnf
# case_insensitive
# source_file
db|dffpipe_bo8.tdf
165053dfbab0ce965855ae149428a9ad
6
# used_port {
q0
-1
3
d0
-1
3
clrn
-1
3
clock
-1
3
}
# end
# entity
alt_synch_pipe_oc8
# storage
db|DE2_NIOS_DEVICE_LED.(22).cnf
db|DE2_NIOS_DEVICE_LED.(22).cnf
# case_insensitive
# source_file
db|alt_synch_pipe_oc8.tdf
c9c9642f95195d3c23e0cff74b5fbc36
6
# used_port {
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clrn
-1
3
clock
-1
3
}
# end
# entity
dffpipe_id9
# storage
db|DE2_NIOS_DEVICE_LED.(23).cnf
db|DE2_NIOS_DEVICE_LED.(23).cnf
# case_insensitive
# source_file
db|dffpipe_id9.tdf
55fbc1c4483b98b792dc22b537e587e5
6
# used_port {
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
clrn
-1
3
clock
-1
3
}
# end
# entity
DM9000A
# storage
db|DE2_NIOS_DEVICE_LED.(25).cnf
db|DE2_NIOS_DEVICE_LED.(25).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
DM9000A.v
f4a41d5814625b575a2f7b48a88aaa8
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
DM9000A_IF
# storage
db|DE2_NIOS_DEVICE_LED.(26).cnf
db|DE2_NIOS_DEVICE_LED.(26).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
DM9000A_IF.v
2b6d9d3ea9fb2983d85f882965b453b7
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
ISP1362
# storage
db|DE2_NIOS_DEVICE_LED.(29).cnf
db|DE2_NIOS_DEVICE_LED.(29).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ISP1362.v
84745c8a18e91724a77c3b61342bc814
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
ISP1362_IF
# storage
db|DE2_NIOS_DEVICE_LED.(30).cnf
db|DE2_NIOS_DEVICE_LED.(30).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ISP1362_IF.v
4e82b153a3787f79d59df44cea3b7c1
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
SD_CLK
# storage
db|DE2_NIOS_DEVICE_LED.(32).cnf
db|DE2_NIOS_DEVICE_LED.(32).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SD_CLK.v
ca796f2bf8cbed0eb4ac1ea1b18606b
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
SD_CMD
# storage
db|DE2_NIOS_DEVICE_LED.(34).cnf
db|DE2_NIOS_DEVICE_LED.(34).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SD_CMD.v
ce24d46e9b12c2a2ed73bc0381f9087
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
SD_DAT
# storage
db|DE2_NIOS_DEVICE_LED.(36).cnf
db|DE2_NIOS_DEVICE_LED.(36).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SD_DAT.v
2da2d720f53f2d267fc54e6ac559
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
SEG7_Display
# storage
db|DE2_NIOS_DEVICE_LED.(38).cnf
db|DE2_NIOS_DEVICE_LED.(38).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SEG7_Display.v
30db6ba3bf801e6df0e7687790f01151
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
SEG7_LUT_8
# storage
db|DE2_NIOS_DEVICE_LED.(39).cnf
db|DE2_NIOS_DEVICE_LED.(39).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SEG7_LUT_8.v
b2cff562a13bcd96a4e2e3dd6c7df8e
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
SEG7_LUT
# storage
db|DE2_NIOS_DEVICE_LED.(40).cnf
db|DE2_NIOS_DEVICE_LED.(40).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SEG7_LUT.v
3b3d255e288f865668e6d661da57411
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
VGA_0
# storage
db|DE2_NIOS_DEVICE_LED.(42).cnf
db|DE2_NIOS_DEVICE_LED.(42).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
VGA_0.v
6a74e89bdd4ba818d9391fe9b8d5d5a
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
VGA_NIOS_CTRL
# storage
db|DE2_NIOS_DEVICE_LED.(43).cnf
db|DE2_NIOS_DEVICE_LED.(43).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
VGA_NIOS_CTRL.v
5e84458ca710d596b1e6726e67691c0
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
RAM_SIZE
1001011000000000000
PARAMETER_BIN
USR
}
# end
# entity
VGA_Controller
# storage
db|DE2_NIOS_DEVICE_LED.(44).cnf
db|DE2_NIOS_DEVICE_LED.(44).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
VGA_Controller.v
0834e99b0bb07d69fde9ed74962bfb
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
H_SYNC_CYC
96
PARAMETER_DEC
DEF
H_SYNC_BACK
48
PARAMETER_DEC
DEF
H_SYNC_ACT
640
PARAMETER_DEC
DEF
H_SYNC_FRONT
16
PARAMETER_DEC
DEF
H_SYNC_TOTAL
800
PARAMETER_DEC
DEF
V_SYNC_CYC
2
PARAMETER_DEC
DEF
V_SYNC_BACK
32
PARAMETER_DEC
DEF
V_SYNC_ACT
480
PARAMETER_DEC
DEF
V_SYNC_FRONT
11
PARAMETER_DEC
DEF
V_SYNC_TOTAL
525
PARAMETER_DEC
DEF
X_START
148
PARAMETER_DEC
DEF
Y_START
34
PARAMETER_DEC
DEF
}
# include_file {
VGA_Param.h
22d76eff94710ac26d957dd18618e6
}
# end
# entity
VGA_OSD_RAM
# storage
db|DE2_NIOS_DEVICE_LED.(45).cnf
db|DE2_NIOS_DEVICE_LED.(45).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
VGA_OSD_RAM.v
d13343d83cd650e7132656823fef1d64
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
Img_RAM
# storage
db|DE2_NIOS_DEVICE_LED.(46).cnf
db|DE2_NIOS_DEVICE_LED.(46).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Img_RAM.v
7e8929c8261b40350b3794a631bd3da
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
altsyncram
# storage
db|DE2_NIOS_DEVICE_LED.(47).cnf
db|DE2_NIOS_DEVICE_LED.(47).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
1
PARAMETER_DEC
USR
WIDTHAD_A
19
PARAMETER_DEC
USR
NUMWORDS_A
307200
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_DEC
USR
WIDTHAD_B
16
PARAMETER_DEC
USR
NUMWORDS_B
38400
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
M4K
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
Img_DATA.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_B
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
BYPASS
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_q7o1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# end
# entity
altsyncram_q7o1
# storage
db|DE2_NIOS_DEVICE_LED.(48).cnf
db|DE2_NIOS_DEVICE_LED.(48).cnf
# case_insensitive
# source_file
db|altsyncram_q7o1.tdf
e55816fdf02bafbcaf775ec5cd730ad
6
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a0
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b15
-1
3
address_b14
-1
3
address_b13
-1
3
address_b12
-1
3
address_b11
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a18
-1
3
address_a17
-1
3
address_a16
-1
3
address_a15
-1
3
address_a14
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
}
# end
# entity
altsyncram_p132
# storage
db|DE2_NIOS_DEVICE_LED.(49).cnf
db|DE2_NIOS_DEVICE_LED.(49).cnf
# case_insensitive
# source_file
db|altsyncram_p132.tdf
37e68498c9a2c926aa6aeb6a56d2fda6
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
data_b0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b18
-1
3
address_b17
-1
3
address_b16
-1
3
address_b15
-1
3
address_b14
-1
3
address_b13
-1
3
address_b12
-1
3
address_b11
-1
3
address_b10
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a15
-1
3
address_a14
-1
3
address_a13
-1
3
address_a12
-1
3
address_a11
-1
3
address_a10
-1
3
address_a1
-1
3
address_a0
-1
3
wren_a
-1
1
data_a7
-1
2
data_a6
-1
2
data_a5
-1
2
data_a4
-1
2
data_a3
-1
2
data_a2
-1
2
data_a1
-1
2
data_a0
-1
2
}
# memory_file {
Img_DATA.hex
3e4a986147a9b27bd5613aedddd34a0
}
# end
# entity
decode_1qa
# storage
db|DE2_NIOS_DEVICE_LED.(50).cnf
db|DE2_NIOS_DEVICE_LED.(50).cnf
# case_insensitive
# source_file
db|decode_1qa.tdf
48bc30db6e4ce445c655dde570fee1
6
# used_port {
eq9
-1
3
eq8
-1
3
eq74
-1
3
eq73
-1
3
eq72
-1
3
eq71
-1
3
eq70
-1
3
eq7
-1
3
eq69
-1
3
eq68
-1
3
eq67
-1
3
eq66
-1
3
eq65
-1
3
eq64
-1
3
eq63
-1
3
eq62
-1
3
eq61
-1
3
eq60
-1
3
eq6
-1
3
eq59
-1
3
eq58
-1
3
eq57
-1
3
eq56
-1
3
eq55
-1
3
eq54
-1
3
eq53
-1
3
eq52
-1
3
eq51
-1
3
eq50
-1
3
eq5
-1
3
eq49
-1
3
eq48
-1
3
eq47
-1
3
eq46
-1
3
eq45
-1
3
eq44
-1
3
eq43
-1
3
eq42
-1
3
eq41
-1
3
eq40
-1
3
eq4
-1
3
eq39
-1
3
eq38
-1
3
eq37
-1
3
eq36
-1
3
eq35
-1
3
eq34
-1
3
eq33
-1
3
eq32
-1
3
eq31
-1
3
eq30
-1
3
eq3
-1
3
eq29
-1
3
eq28
-1
3
eq27
-1
3
eq26
-1
3
eq25
-1
3
eq24
-1
3
eq23
-1
3
eq22
-1
3
eq21
-1
3
eq20
-1
3
eq2
-1
3
eq19
-1
3
eq18
-1
3
eq17
-1
3
eq16
-1
3
eq15
-1
3
eq14
-1
3
eq13
-1
3
eq12
-1
3
eq11
-1
3
eq10
-1
3
eq1
-1
3
eq0
-1
3
enable
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
}
# end
# entity
decode_1qa
# storage
db|DE2_NIOS_DEVICE_LED.(51).cnf
db|DE2_NIOS_DEVICE_LED.(51).cnf
# case_insensitive
# source_file
db|decode_1qa.tdf
48bc30db6e4ce445c655dde570fee1
6
# used_port {
eq9
-1
3
eq8
-1
3
eq74
-1
3
eq73
-1
3
eq72
-1
3
eq71
-1
3
eq70
-1
3
eq7
-1
3
eq69
-1
3
eq68
-1
3
eq67
-1
3
eq66
-1
3
eq65
-1
3
eq64
-1
3
eq63
-1
3
eq62
-1
3
eq61
-1
3
eq60
-1
3
eq6
-1
3
eq59
-1
3
eq58
-1
3
eq57
-1
3
eq56
-1
3
eq55
-1
3
eq54
-1
3
eq53
-1
3
eq52
-1
3
eq51
-1
3
eq50
-1
3
eq5
-1
3
eq49
-1
3
eq48
-1
3
eq47
-1
3
eq46
-1
3
eq45
-1
3
eq44
-1
3
eq43
-1
3
eq42
-1
3
eq41
-1
3
eq40
-1
3
eq4
-1
3
eq39
-1
3
eq38
-1
3
eq37
-1
3
eq36
-1
3
eq35
-1
3
eq34
-1
3
eq33
-1
3
eq32
-1
3
eq31
-1
3
eq30
-1
3
eq3
-1
3
eq29
-1
3
eq28
-1
3
eq27
-1
3
eq26
-1
3
eq25
-1
3
eq24
-1
3
eq23
-1
3
eq22
-1
3
eq21
-1
3
eq20
-1
3
eq2
-1
3
eq19
-1
3
eq18
-1
3
eq17
-1
3
eq16
-1
3
eq15
-1
3
eq14
-1
3
eq13
-1
3
eq12
-1
3
eq11
-1
3
eq10
-1
3
eq1
-1
3
eq0
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
enable
-1
2
}
# end
# entity
mux_hkb
# storage
db|DE2_NIOS_DEVICE_LED.(52).cnf
db|DE2_NIOS_DEVICE_LED.(52).cnf
# case_insensitive
# source_file
db|mux_hkb.tdf
7150f9fb82912877e9ad4f67182ba6f3
6
# used_port {
sel6
-1
3
sel5
-1
3
sel4
-1
3
sel3
-1
3
sel2
-1
3
sel1
-1
3
sel0
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
data99
-1
3
data98
-1
3
data97
-1
3
data96
-1
3
data95
-1
3
data94
-1
3
data93
-1
3
data92
-1
3
data91
-1
3
data90
-1
3
data9
-1
3
data89
-1
3
data88
-1
3
data87
-1
3
data86
-1
3
data85
-1
3
data84
-1
3
data83
-1
3
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-1
3
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-1
3
data80
-1
3
data8
-1
3
data79
-1
3
data78
-1
3
data77
-1
3
data76
-1
3
data75
-1
3
data74
-1
3
data73
-1
3
data72
-1
3
data71
-1
3
data70
-1
3
data7
-1
3
data69
-1
3
data68
-1
3
data67
-1
3
data66
-1
3
data65
-1
3
data64
-1
3
data63
-1
3
data62
-1
3
data61
-1
3
data60
-1
3
data6
-1
3
data599
-1
3
data598
-1
3
data597
-1
3
data596
-1
3
data595
-1
3
data594
-1
3
data593
-1
3
data592
-1
3
data591
-1
3
data590
-1
3
data59
-1
3
data589
-1
3
data588
-1
3
data587
-1
3
data586
-1
3
data585
-1
3
data584
-1
3
data583
-1
3
data582
-1
3
data581
-1
3
data580
-1
3
data58
-1
3
data579
-1
3
data578
-1
3
data577
-1
3
data576
-1
3
data575
-1
3
data574
-1
3
data573
-1
3
data572
-1
3
data571
-1
3
data570
-1
3
data57
-1
3
data569
-1
3
data568
-1
3
data567
-1
3
data566
-1
3
data565
-1
3
data564
-1
3
data563
-1
3
data562
-1
3
data561
-1
3
data560
-1
3
data56
-1
3
data559
-1
3
data558
-1
3
data557
-1
3
data556
-1
3
data555
-1
3
data554
-1
3
data553
-1
3
data552
-1
3
data551
-1
3
data550
-1
3
data55
-1
3
data549
-1
3
data548
-1
3
data547
-1
3
data546
-1
3
data545
-1
3
data544
-1
3
data543
-1
3
data542
-1
3
data541
-1
3
data540
-1
3
data54
-1
3
data539
-1
3
data538
-1
3
data537
-1
3
data536
-1
3
data535
-1
3
data534
-1
3
data533
-1
3
data532
-1
3
data531
-1
3
data530
-1
3
data53
-1
3
data529
-1
3
data528
-1
3
data527
-1
3
data526
-1
3
data525
-1
3
data524
-1
3
data523
-1
3
data522
-1
3
data521
-1
3
data520
-1
3
data52
-1
3
data519
-1
3
data518
-1
3
data517
-1
3
data516
-1
3
data515
-1
3
data514
-1
3
data513
-1
3
data512
-1
3
data511
-1
3
data510
-1
3
data51
-1
3
data509
-1
3
data508
-1
3
data507
-1
3
data506
-1
3
data505
-1
3
data504
-1
3
data503
-1
3
data502
-1
3
data501
-1
3
data500
-1
3
data50
-1
3
data5
-1
3
data499
-1
3
data498
-1
3
data497
-1
3
data496
-1
3
data495
-1
3
data494
-1
3
data493
-1
3
data492
-1
3
data491
-1
3
data490
-1
3
data49
-1
3
data489
-1
3
data488
-1
3
data487
-1
3
data486
-1
3
data485
-1
3
data484
-1
3
data483
-1
3
data482
-1
3
data481
-1
3
data480
-1
3
data48
-1
3
data479
-1
3
data478
-1
3
data477
-1
3
data476
-1
3
data475
-1
3
data474
-1
3
data473
-1
3
data472
-1
3
data471
-1
3
data470
-1
3
data47
-1
3
data469
-1
3
data468
-1
3
data467
-1
3
data466
-1
3
data465
-1
3
data464
-1
3
data463
-1
3
data462
-1
3
data461
-1
3
data460
-1
3
data46
-1
3
data459
-1
3
data458
-1
3
data457
-1
3
data456
-1
3
data455
-1
3
data454
-1
3
data453
-1
3
data452
-1
3
data451
-1
3
data450
-1
3
data45
-1
3
data449
-1
3
data448
-1
3
data447
-1
3
data446
-1
3
data445
-1
3
data444
-1
3
data443
-1
3
data442
-1
3
data441
-1
3
data440
-1
3
data44
-1
3
data439
-1
3
data438
-1
3
data437
-1
3
data436
-1
3
data435
-1
3
data434
-1
3
data433
-1
3
data432
-1
3
data431
-1
3
data430
-1
3
data43
-1
3
data429
-1
3
data428
-1
3
data427
-1
3
data426
-1
3
data425
-1
3
data424
-1
3
data423
-1
3
data422
-1
3
data421
-1
3
data420
-1
3
data42
-1
3
data419
-1
3
data418
-1
3
data417
-1
3
data416
-1
3
data415
-1
3
data414
-1
3
data413
-1
3
data412
-1
3
data411
-1
3
data410
-1
3
data41
-1
3
data409
-1
3
data408
-1
3
data407
-1
3
data406
-1
3
data405
-1
3
data404
-1
3
data403
-1
3
data402
-1
3
data401
-1
3
data400
-1
3
data40
-1
3
data4
-1
3
data399
-1
3
data398
-1
3
data397
-1
3
data396
-1
3
data395
-1
3
data394
-1
3
data393
-1
3
data392
-1
3
data391
-1
3
data390
-1
3
data39
-1
3
data389
-1
3
data388
-1
3
data387
-1
3
data386
-1
3
data385
-1
3
data384
-1
3
data383
-1
3
data382
-1
3
data381
-1
3
data380
-1
3
data38
-1
3
data379
-1
3
data378
-1
3
data377
-1
3
data376
-1
3
data375
-1
3
data374
-1
3
data373
-1
3
data372
-1
3
data371
-1
3
data370
-1
3
data37
-1
3
data369
-1
3
data368
-1
3
data367
-1
3
data366
-1
3
data365
-1
3
data364
-1
3
data363
-1
3
data362
-1
3
data361
-1
3
data360
-1
3
data36
-1
3
data359
-1
3
data358
-1
3
data357
-1
3
data356
-1
3
data355
-1
3
data354
-1
3
data353
-1
3
data352
-1
3
data351
-1
3
data350
-1
3
data35
-1
3
data349
-1
3
data348
-1
3
data347
-1
3
data346
-1
3
data345
-1
3
data344
-1
3
data343
-1
3
data342
-1
3
data341
-1
3
data340
-1
3
data34
-1
3
data339
-1
3
data338
-1
3
data337
-1
3
data336
-1
3
data335
-1
3
data334
-1
3
data333
-1
3
data332
-1
3
data331
-1
3
data330
-1
3
data33
-1
3
data329
-1
3
data328
-1
3
data327
-1
3
data326
-1
3
data325
-1
3
data324
-1
3
data323
-1
3
data322
-1
3
data321
-1
3
data320
-1
3
data32
-1
3
data319
-1
3
data318
-1
3
data317
-1
3
data316
-1
3
data315
-1
3
data314
-1
3
data313
-1
3
data312
-1
3
data311
-1
3
data310
-1
3
data31
-1
3
data309
-1
3
data308
-1
3
data307
-1
3
data306
-1
3
data305
-1
3
data304
-1
3
data303
-1
3
data302
-1
3
data301
-1
3
data300
-1
3
data30
-1
3
data3
-1
3
data299
-1
3
data298
-1
3
data297
-1
3
data296
-1
3
data295
-1
3
data294
-1
3
data293
-1
3
data292
-1
3
data291
-1
3
data290
-1
3
data29
-1
3
data289
-1
3
data288
-1
3
data287
-1
3
data286
-1
3
data285
-1
3
data284
-1
3
data283
-1
3
data282
-1
3
data281
-1
3
data280
-1
3
data28
-1
3
data279
-1
3
data278
-1
3
data277
-1
3
data276
-1
3
data275
-1
3
data274
-1
3
data273
-1
3
data272
-1
3
data271
-1
3
data270
-1
3
data27
-1
3
data269
-1
3
data268
-1
3
data267
-1
3
data266
-1
3
data265
-1
3
data264
-1
3
data263
-1
3
data262
-1
3
data261
-1
3
data260
-1
3
data26
-1
3
data259
-1
3
data258
-1
3
data257
-1
3
data256
-1
3
data255
-1
3
data254
-1
3
data253
-1
3
data252
-1
3
data251
-1
3
data250
-1
3
data25
-1
3
data249
-1
3
data248
-1
3
data247
-1
3
data246
-1
3
data245
-1
3
data244
-1
3
data243
-1
3
data242
-1
3
data241
-1
3
data240
-1
3
data24
-1
3
data239
-1
3
data238
-1
3
data237
-1
3
data236
-1
3
data235
-1
3
data234
-1
3
data233
-1
3
data232
-1
3
data231
-1
3
data230
-1
3
data23
-1
3
data229
-1
3
data228
-1
3
data227
-1
3
data226
-1
3
data225
-1
3
data224
-1
3
data223
-1
3
data222
-1
3
data221
-1
3
data220
-1
3
data22
-1
3
data219
-1
3
data218
-1
3
data217
-1
3
data216
-1
3
data215
-1
3
data214
-1
3
data213
-1
3
data212
-1
3
data211
-1
3
data210
-1
3
data21
-1
3
data209
-1
3
data208
-1
3
data207
-1
3
data206
-1
3
data205
-1
3
data204
-1
3
data203
-1
3
data202
-1
3
data201
-1
3
data200
-1
3
data20
-1
3
data2
-1
3
data199
-1
3
data198
-1
3
data197
-1
3
data196
-1
3
data195
-1
3
data194
-1
3
data193
-1
3
data192
-1
3
data191
-1
3
data190
-1
3
data19
-1
3
data189
-1
3
data188
-1
3
data187
-1
3
data186
-1
3
data185
-1
3
data184
-1
3
data183
-1
3
data182
-1
3
data181
-1
3
data180
-1
3
data18
-1
3
data179
-1
3
data178
-1
3
data177
-1
3
data176
-1
3
data175
-1
3
data174
-1
3
data173
-1
3
data172
-1
3
data171
-1
3
data170
-1
3
data17
-1
3
data169
-1
3
data168
-1
3
data167
-1
3
data166
-1
3
data165
-1
3
data164
-1
3
data163
-1
3
data162
-1
3
data161
-1
3
data160
-1
3
data16
-1
3
data159
-1
3
data158
-1
3
data157
-1
3
data156
-1
3
data155
-1
3
data154
-1
3
data153
-1
3
data152
-1
3
data151
-1
3
data150
-1
3
data15
-1
3
data149
-1
3
data148
-1
3
data147
-1
3
data146
-1
3
data145
-1
3
data144
-1
3
data143
-1
3
data142
-1
3
data141
-1
3
data140
-1
3
data14
-1
3
data139
-1
3
data138
-1
3
data137
-1
3
data136
-1
3
data135
-1
3
data134
-1
3
data133
-1
3
data132
-1
3
data131
-1
3
data130
-1
3
data13
-1
3
data129
-1
3
data128
-1
3
data127
-1
3
data126
-1
3
data125
-1
3
data124
-1
3
data123
-1
3
data122
-1
3
data121
-1
3
data120
-1
3
data12
-1
3
data119
-1
3
data118
-1
3
data117
-1
3
data116
-1
3
data115
-1
3
data114
-1
3
data113
-1
3
data112
-1
3
data111
-1
3
data110
-1
3
data11
-1
3
data109
-1
3
data108
-1
3
data107
-1
3
data106
-1
3
data105
-1
3
data104
-1
3
data103
-1
3
data102
-1
3
data101
-1
3
data100
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# end
# entity
mux_akb
# storage
db|DE2_NIOS_DEVICE_LED.(53).cnf
db|DE2_NIOS_DEVICE_LED.(53).cnf
# case_insensitive
# source_file
db|mux_akb.tdf
c8c9b3cf7ecf1c249fd5992720411146
6
# used_port {
sel6
-1
3
sel5
-1
3
sel4
-1
3
sel3
-1
3
sel2
-1
3
sel1
-1
3
sel0
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data74
-1
3
data73
-1
3
data72
-1
3
data71
-1
3
data70
-1
3
data7
-1
3
data69
-1
3
data68
-1
3
data67
-1
3
data66
-1
3
data65
-1
3
data64
-1
3
data63
-1
3
data62
-1
3
data61
-1
3
data60
-1
3
data6
-1
3
data59
-1
3
data58
-1
3
data57
-1
3
data56
-1
3
data55
-1
3
data54
-1
3
data53
-1
3
data52
-1
3
data51
-1
3
data50
-1
3
data5
-1
3
data49
-1
3
data48
-1
3
data47
-1
3
data46
-1
3
data45
-1
3
data44
-1
3
data43
-1
3
data42
-1
3
data41
-1
3
data40
-1
3
data4
-1
3
data39
-1
3
data38
-1
3
data37
-1
3
data36
-1
3
data35
-1
3
data34
-1
3
data33
-1
3
data32
-1
3
data31
-1
3
data30
-1
3
data3
-1
3
data29
-1
3
data28
-1
3
data27
-1
3
data26
-1
3
data25
-1
3
data24
-1
3
data23
-1
3
data22
-1
3
data21
-1
3
data20
-1
3
data2
-1
3
data19
-1
3
data18
-1
3
data17
-1
3
data16
-1
3
data15
-1
3
data14
-1
3
data13
-1
3
data12
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# end
# entity
button_pio
# storage
db|DE2_NIOS_DEVICE_LED.(55).cnf
db|DE2_NIOS_DEVICE_LED.(55).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
button_pio.v
6cec94df2e44a4ccb05164c41847fdc
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|button_pio:the_button_pio
}
# end
# entity
clock_0
# storage
db|DE2_NIOS_DEVICE_LED.(58).cnf
db|DE2_NIOS_DEVICE_LED.(58).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_0.v
f37dbd3d577c7f5b25328196d9deba
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_0:the_clock_0
}
# end
# entity
clock_0_master_read_done_sync_module
# storage
db|DE2_NIOS_DEVICE_LED.(59).cnf
db|DE2_NIOS_DEVICE_LED.(59).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_0.v
f37dbd3d577c7f5b25328196d9deba
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_0:the_clock_0|clock_0_master_read_done_sync_module:clock_0_master_read_done_sync
}
# end
# entity
clock_0_master_write_done_sync_module
# storage
db|DE2_NIOS_DEVICE_LED.(60).cnf
db|DE2_NIOS_DEVICE_LED.(60).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_0.v
f37dbd3d577c7f5b25328196d9deba
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_0:the_clock_0|clock_0_master_write_done_sync_module:clock_0_master_write_done_sync
}
# end
# entity
clock_0_edge_to_pulse
# storage
db|DE2_NIOS_DEVICE_LED.(61).cnf
db|DE2_NIOS_DEVICE_LED.(61).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_0.v
f37dbd3d577c7f5b25328196d9deba
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_0:the_clock_0|clock_0_edge_to_pulse:read_done_edge_to_pulse
system_0:u0|clock_0:the_clock_0|clock_0_edge_to_pulse:write_done_edge_to_pulse
system_0:u0|clock_0:the_clock_0|clock_0_edge_to_pulse:read_request_edge_to_pulse
system_0:u0|clock_0:the_clock_0|clock_0_edge_to_pulse:write_request_edge_to_pulse
}
# end
# entity
clock_0_slave_FSM
# storage
db|DE2_NIOS_DEVICE_LED.(62).cnf
db|DE2_NIOS_DEVICE_LED.(62).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_0.v
f37dbd3d577c7f5b25328196d9deba
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_0:the_clock_0|clock_0_slave_FSM:slave_FSM
}
# end
# entity
clock_0_slave_read_request_sync_module
# storage
db|DE2_NIOS_DEVICE_LED.(63).cnf
db|DE2_NIOS_DEVICE_LED.(63).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_0.v
f37dbd3d577c7f5b25328196d9deba
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_0:the_clock_0|clock_0_slave_read_request_sync_module:clock_0_slave_read_request_sync
}
# end
# entity
clock_0_slave_write_request_sync_module
# storage
db|DE2_NIOS_DEVICE_LED.(64).cnf
db|DE2_NIOS_DEVICE_LED.(64).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_0.v
f37dbd3d577c7f5b25328196d9deba
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_0:the_clock_0|clock_0_slave_write_request_sync_module:clock_0_slave_write_request_sync
}
# end
# entity
clock_0_master_FSM
# storage
db|DE2_NIOS_DEVICE_LED.(65).cnf
db|DE2_NIOS_DEVICE_LED.(65).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_0.v
f37dbd3d577c7f5b25328196d9deba
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_0:the_clock_0|clock_0_master_FSM:master_FSM
}
# end
# entity
clock_0_bit_pipe
# storage
db|DE2_NIOS_DEVICE_LED.(66).cnf
db|DE2_NIOS_DEVICE_LED.(66).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_0.v
f37dbd3d577c7f5b25328196d9deba
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_0:the_clock_0|clock_0_bit_pipe:endofpacket_bit_pipe
}
# end
# entity
clock_1
# storage
db|DE2_NIOS_DEVICE_LED.(69).cnf
db|DE2_NIOS_DEVICE_LED.(69).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_1.v
944a8b32139398abce43ad7b7fedb0bc
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_1:the_clock_1
}
# end
# entity
clock_1_master_read_done_sync_module
# storage
db|DE2_NIOS_DEVICE_LED.(70).cnf
db|DE2_NIOS_DEVICE_LED.(70).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_1.v
944a8b32139398abce43ad7b7fedb0bc
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_1:the_clock_1|clock_1_master_read_done_sync_module:clock_1_master_read_done_sync
}
# end
# entity
clock_1_master_write_done_sync_module
# storage
db|DE2_NIOS_DEVICE_LED.(71).cnf
db|DE2_NIOS_DEVICE_LED.(71).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_1.v
944a8b32139398abce43ad7b7fedb0bc
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync
}
# end
# entity
clock_1_edge_to_pulse
# storage
db|DE2_NIOS_DEVICE_LED.(72).cnf
db|DE2_NIOS_DEVICE_LED.(72).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_1.v
944a8b32139398abce43ad7b7fedb0bc
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_1:the_clock_1|clock_1_edge_to_pulse:read_done_edge_to_pulse
system_0:u0|clock_1:the_clock_1|clock_1_edge_to_pulse:write_done_edge_to_pulse
system_0:u0|clock_1:the_clock_1|clock_1_edge_to_pulse:read_request_edge_to_pulse
system_0:u0|clock_1:the_clock_1|clock_1_edge_to_pulse:write_request_edge_to_pulse
}
# end
# entity
clock_1_slave_FSM
# storage
db|DE2_NIOS_DEVICE_LED.(73).cnf
db|DE2_NIOS_DEVICE_LED.(73).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_1.v
944a8b32139398abce43ad7b7fedb0bc
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_1:the_clock_1|clock_1_slave_FSM:slave_FSM
}
# end
# entity
clock_1_slave_read_request_sync_module
# storage
db|DE2_NIOS_DEVICE_LED.(74).cnf
db|DE2_NIOS_DEVICE_LED.(74).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_1.v
944a8b32139398abce43ad7b7fedb0bc
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_1:the_clock_1|clock_1_slave_read_request_sync_module:clock_1_slave_read_request_sync
}
# end
# entity
clock_1_slave_write_request_sync_module
# storage
db|DE2_NIOS_DEVICE_LED.(75).cnf
db|DE2_NIOS_DEVICE_LED.(75).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_1.v
944a8b32139398abce43ad7b7fedb0bc
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_1:the_clock_1|clock_1_slave_write_request_sync_module:clock_1_slave_write_request_sync
}
# end
# entity
clock_1_master_FSM
# storage
db|DE2_NIOS_DEVICE_LED.(76).cnf
db|DE2_NIOS_DEVICE_LED.(76).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_1.v
944a8b32139398abce43ad7b7fedb0bc
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_1:the_clock_1|clock_1_master_FSM:master_FSM
}
# end
# entity
clock_1_bit_pipe
# storage
db|DE2_NIOS_DEVICE_LED.(77).cnf
db|DE2_NIOS_DEVICE_LED.(77).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clock_1.v
944a8b32139398abce43ad7b7fedb0bc
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_1:the_clock_1|clock_1_bit_pipe:endofpacket_bit_pipe
}
# end
# entity
cpu_0_test_bench
# storage
db|DE2_NIOS_DEVICE_LED.(82).cnf
db|DE2_NIOS_DEVICE_LED.(82).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0_test_bench.v
763262959319fc1297d7301706afaeb
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench
}
# end
# entity
altsyncram
# storage
db|DE2_NIOS_DEVICE_LED.(84).cnf
db|DE2_NIOS_DEVICE_LED.(84).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
1024
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
10
PARAMETER_DEC
USR
NUMWORDS_B
1024
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_cub1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
clocken0
-1
2
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_cub1
# storage
db|DE2_NIOS_DEVICE_LED.(85).cnf
db|DE2_NIOS_DEVICE_LED.(85).cnf
# case_insensitive
# source_file
db|altsyncram_cub1.tdf
5384f44fa7a826bb9962968853ec85fd
6
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated
}
# end
# entity
altsyncram_k1l1
# storage
db|DE2_NIOS_DEVICE_LED.(86).cnf
db|DE2_NIOS_DEVICE_LED.(86).cnf
# case_insensitive
# source_file
db|altsyncram_k1l1.tdf
551f269030cb5e593abf90ab123459d2
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b31
-1
3
data_b30
-1
3
data_b3
-1
3
data_b29
-1
3
data_b28
-1
3
data_b27
-1
3
data_b26
-1
3
data_b25
-1
3
data_b24
-1
3
data_b23
-1
3
data_b22
-1
3
data_b21
-1
3
data_b20
-1
3
data_b2
-1
3
data_b19
-1
3
data_b18
-1
3
data_b17
-1
3
data_b16
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b9
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
wren_a
-1
1
data_a9
-1
2
data_a8
-1
2
data_a7
-1
2
data_a6
-1
2
data_a5
-1
2
data_a4
-1
2
data_a31
-1
2
data_a30
-1
2
data_a3
-1
2
data_a29
-1
2
data_a28
-1
2
data_a27
-1
2
data_a26
-1
2
data_a25
-1
2
data_a24
-1
2
data_a23
-1
2
data_a22
-1
2
data_a21
-1
2
data_a20
-1
2
data_a2
-1
2
data_a19
-1
2
data_a18
-1
2
data_a17
-1
2
data_a16
-1
2
data_a15
-1
2
data_a14
-1
2
data_a13
-1
2
data_a12
-1
2
data_a11
-1
2
data_a10
-1
2
data_a1
-1
2
data_a0
-1
2
}
# memory_file {
none
0
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data|altsyncram:the_altsyncram|altsyncram_cub1:auto_generated|altsyncram_k1l1:altsyncram1
}
# end
# entity
altsyncram
# storage
db|DE2_NIOS_DEVICE_LED.(88).cnf
db|DE2_NIOS_DEVICE_LED.(88).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
20
PARAMETER_DEC
USR
WIDTHAD_A
7
PARAMETER_DEC
USR
NUMWORDS_A
128
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
20
PARAMETER_DEC
USR
WIDTHAD_B
7
PARAMETER_DEC
USR
NUMWORDS_B
128
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
cpu_0_ic_tag_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_tke1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
clocken0
-1
2
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_tke1
# storage
db|DE2_NIOS_DEVICE_LED.(89).cnf
db|DE2_NIOS_DEVICE_LED.(89).cnf
# case_insensitive
# source_file
db|altsyncram_tke1.tdf
6912a742f2a1418ca7c520ec7ed1ecd8
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_0_ic_tag_ram.mif
f8f79ec08bfecffe63b41fdd54732c
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag|altsyncram:the_altsyncram|altsyncram_tke1:auto_generated
}
# end
# entity
altsyncram
# storage
db|DE2_NIOS_DEVICE_LED.(91).cnf
db|DE2_NIOS_DEVICE_LED.(91).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
2
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
2
PARAMETER_DEC
USR
WIDTHAD_B
8
PARAMETER_DEC
USR
NUMWORDS_B
256
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
cpu_0_bht_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_q8e1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
clocken0
-1
2
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_q8e1
# storage
db|DE2_NIOS_DEVICE_LED.(92).cnf
db|DE2_NIOS_DEVICE_LED.(92).cnf
# case_insensitive
# source_file
db|altsyncram_q8e1.tdf
d81f11c3163919a095f3ea8cd849af37
6
# used_port {
wren_a
-1
3
q_b1
-1
3
q_b0
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated
}
# end
# entity
altsyncram_pfn1
# storage
db|DE2_NIOS_DEVICE_LED.(93).cnf
db|DE2_NIOS_DEVICE_LED.(93).cnf
# case_insensitive
# source_file
db|altsyncram_pfn1.tdf
977ea767e7695427c7940d715222d11
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
q_a1
-1
3
q_a0
-1
3
data_b1
-1
3
data_b0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
wren_a
-1
1
data_a1
-1
2
data_a0
-1
2
}
# memory_file {
cpu_0_bht_ram.mif
114c797a04d1946467f2ad12954496
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht|altsyncram:the_altsyncram|altsyncram_q8e1:auto_generated|altsyncram_pfn1:altsyncram1
}
# end
# entity
altsyncram
# storage
db|DE2_NIOS_DEVICE_LED.(95).cnf
db|DE2_NIOS_DEVICE_LED.(95).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
5
PARAMETER_DEC
USR
NUMWORDS_A
32
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
5
PARAMETER_DEC
USR
NUMWORDS_B
32
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
cpu_0_rf_ram_a.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_4be1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
clocken0
-1
2
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_4be1
# storage
db|DE2_NIOS_DEVICE_LED.(96).cnf
db|DE2_NIOS_DEVICE_LED.(96).cnf
# case_insensitive
# source_file
db|altsyncram_4be1.tdf
3957391989d7e50186cdaeebdf3ec3d
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_0_rf_ram_a.mif
55d713de4db17accc269d4dfa42c9c44
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a|altsyncram:the_altsyncram|altsyncram_4be1:auto_generated
}
# end
# entity
altsyncram
# storage
db|DE2_NIOS_DEVICE_LED.(98).cnf
db|DE2_NIOS_DEVICE_LED.(98).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
5
PARAMETER_DEC
USR
NUMWORDS_A
32
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
5
PARAMETER_DEC
USR
NUMWORDS_B
32
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
cpu_0_rf_ram_b.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_5be1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
clocken0
-1
2
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_5be1
# storage
db|DE2_NIOS_DEVICE_LED.(99).cnf
db|DE2_NIOS_DEVICE_LED.(99).cnf
# case_insensitive
# source_file
db|altsyncram_5be1.tdf
e1b3a6a0644ba53af2bb4a29a88b543c
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_0_rf_ram_b.mif
55d713de4db17accc269d4dfa42c9c44
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b|altsyncram:the_altsyncram|altsyncram_5be1:auto_generated
}
# end
# entity
altsyncram
# storage
db|DE2_NIOS_DEVICE_LED.(101).cnf
db|DE2_NIOS_DEVICE_LED.(101).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
15
PARAMETER_DEC
USR
WIDTHAD_A
9
PARAMETER_DEC
USR
NUMWORDS_A
512
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
15
PARAMETER_DEC
USR
WIDTHAD_B
9
PARAMETER_DEC
USR
NUMWORDS_B
512
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
cpu_0_dc_tag_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_vf22
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
q_b
-1
3
q_a
-1
3
data_b
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
wren_a
-1
1
data_a
-1
1
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_vf22
# storage
db|DE2_NIOS_DEVICE_LED.(102).cnf
db|DE2_NIOS_DEVICE_LED.(102).cnf
# case_insensitive
# source_file
db|altsyncram_vf22.tdf
53e18bcbed7ea4f5d1bf507edbebad2a
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b3
-1
3
data_b2
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_0_dc_tag_ram.mif
b74b747a7d26bbc1d719ff004df737
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag|altsyncram:the_altsyncram|altsyncram_vf22:auto_generated
}
# end
# entity
altsyncram
# storage
db|DE2_NIOS_DEVICE_LED.(104).cnf
db|DE2_NIOS_DEVICE_LED.(104).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
9
PARAMETER_DEC
USR
NUMWORDS_A
512
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
9
PARAMETER_DEC
USR
NUMWORDS_B
512
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
4
PARAMETER_DEC
USR
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_a422
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
q_b
-1
3
q_a
-1
3
data_b
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
byteena_b
-1
3
address_b
-1
3
address_a
-1
3
wren_a
-1
1
data_a
-1
1
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_a422
# storage
db|DE2_NIOS_DEVICE_LED.(105).cnf
db|DE2_NIOS_DEVICE_LED.(105).cnf
# case_insensitive
# source_file
db|altsyncram_a422.tdf
ae8a628bea25c77cf851c6ea181f7ace
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b31
-1
3
data_b30
-1
3
data_b3
-1
3
data_b29
-1
3
data_b28
-1
3
data_b27
-1
3
data_b26
-1
3
data_b25
-1
3
data_b24
-1
3
data_b23
-1
3
data_b22
-1
3
data_b21
-1
3
data_b20
-1
3
data_b2
-1
3
data_b19
-1
3
data_b18
-1
3
data_b17
-1
3
data_b16
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
byteena_b3
-1
3
byteena_b2
-1
3
byteena_b1
-1
3
byteena_b0
-1
3
address_b8
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data|altsyncram:the_altsyncram|altsyncram_a422:auto_generated
}
# end
# entity
cpu_0_mult_cell
# storage
db|DE2_NIOS_DEVICE_LED.(106).cnf
db|DE2_NIOS_DEVICE_LED.(106).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0_mult_cell.v
a7695199bf34bfa7966c961c2b5cd1
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell
}
# end
# entity
altmult_add
# storage
db|DE2_NIOS_DEVICE_LED.(107).cnf
db|DE2_NIOS_DEVICE_LED.(107).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altmult_add.tdf
b0d21f7d73b7468b4efdda766d24885
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
NUMBER_OF_MULTIPLIERS
1
PARAMETER_DEC
USR
WIDTH_A
16
PARAMETER_DEC
USR
WIDTH_B
16
PARAMETER_DEC
USR
WIDTH_RESULT
32
PARAMETER_DEC
USR
INPUT_REGISTER_A0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_ACLR_A0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A0
DATAA
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_A1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A1
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A2
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A3
DATAA
PARAMETER_UNKNOWN
DEF
REPRESENTATION_A
UNSIGNED
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
SIGNED_ACLR_A
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_PIPELINE_REGISTER_A
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_ACLR_A
ACLR0
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_B0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_ACLR_B0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B0
DATAB
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_B1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B1
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B2
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B3
DATAB
PARAMETER_UNKNOWN
DEF
REPRESENTATION_B
UNSIGNED
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
SIGNED_ACLR_B
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_PIPELINE_REGISTER_B
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_ACLR_B
ACLR0
PARAMETER_UNKNOWN
USR
MULTIPLIER_REGISTER0
CLOCK0
PARAMETER_UNKNOWN
USR
MULTIPLIER_ACLR0
ACLR0
PARAMETER_UNKNOWN
USR
MULTIPLIER_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER1_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_REGISTER1
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1
ACLR0
PARAMETER_UNKNOWN
USR
MULTIPLIER_REGISTER2
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR2
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER3_DIRECTION
UNUSED
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER23_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER23_SATURATION
NO
PARAMETER_UNKNOWN
DEF
ADDER1_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDER3_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
PORT_MULT0_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT1_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT2_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT3_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
PORT_SIGNA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SIGNB
PORT_UNUSED
PARAMETER_UNKNOWN
USR
OUTPUT_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
USR
OUTPUT_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
EXTRA_LATENCY
0
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_CIRCUITRY
YES
PARAMETER_UNKNOWN
USR
DSP_BLOCK_BALANCING
AUTO
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
mult_add_4cr2
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
}
# used_port {
result
-1
3
datab
-1
3
dataa
-1
3
clock0
-1
3
aclr0
-1
3
ena0
-1
2
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|stratix_mac_mult.inc
37fae19b7be3fd367b8beebe8242bb70
..|..|..|altera|quartus60|libraries|megafunctions|stratix_mac_out.inc
7e6e79cdf4a1237186d7c89ebab37e
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1
}
# end
# entity
mult_add_4cr2
# storage
db|DE2_NIOS_DEVICE_LED.(108).cnf
db|DE2_NIOS_DEVICE_LED.(108).cnf
# case_insensitive
# source_file
db|mult_add_4cr2.tdf
ad21bb65748178a6e57d2f8695ee8a61
6
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result31
-1
3
result30
-1
3
result3
-1
3
result29
-1
3
result28
-1
3
result27
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock0
-1
3
aclr0
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated
}
# end
# entity
ded_mult_2o81
# storage
db|DE2_NIOS_DEVICE_LED.(109).cnf
db|DE2_NIOS_DEVICE_LED.(109).cnf
# case_insensitive
# source_file
db|ded_mult_2o81.tdf
3ff49b1dee75e9fa4459464da7ce3f6
6
# user_parameter {
dataa_width
0
PARAMETER_UNKNOWN
DEF
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result31
-1
3
result30
-1
3
result3
-1
3
result29
-1
3
result28
-1
3
result27
-1
3
result26
-1
3
result25
-1
3
result24
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
ena0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock0
-1
3
aclr0
-1
3
aclr3
-1
1
aclr2
-1
1
aclr1
-1
1
ena3
-1
2
ena2
-1
2
ena1
-1
2
clock3
-1
2
clock2
-1
2
clock1
-1
2
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1
}
# end
# entity
dffpipe_93c
# storage
db|DE2_NIOS_DEVICE_LED.(110).cnf
db|DE2_NIOS_DEVICE_LED.(110).cnf
# case_insensitive
# source_file
db|dffpipe_93c.tdf
8f879e7b16fcb56b194f60a87e51ade
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q31
-1
3
q30
-1
3
q3
-1
3
q29
-1
3
q28
-1
3
q27
-1
3
q26
-1
3
q25
-1
3
q24
-1
3
q23
-1
3
q22
-1
3
q21
-1
3
q20
-1
3
q2
-1
3
q19
-1
3
q18
-1
3
q17
-1
3
q16
-1
3
q15
-1
3
q14
-1
3
q13
-1
3
q12
-1
3
q11
-1
3
q10
-1
3
q1
-1
3
q0
-1
3
d9
-1
3
d8
-1
3
d7
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d31
-1
3
d30
-1
3
d3
-1
3
d29
-1
3
d28
-1
3
d27
-1
3
d26
-1
3
d25
-1
3
d24
-1
3
d23
-1
3
d22
-1
3
d21
-1
3
d20
-1
3
d2
-1
3
d19
-1
3
d18
-1
3
d17
-1
3
d16
-1
3
d15
-1
3
d14
-1
3
d13
-1
3
d12
-1
3
d11
-1
3
d10
-1
3
d1
-1
3
d0
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_1|mult_add_4cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated|ded_mult_2o81:ded_mult1|dffpipe_93c:pre_result
}
# end
# entity
altmult_add
# storage
db|DE2_NIOS_DEVICE_LED.(111).cnf
db|DE2_NIOS_DEVICE_LED.(111).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altmult_add.tdf
b0d21f7d73b7468b4efdda766d24885
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
NUMBER_OF_MULTIPLIERS
1
PARAMETER_DEC
USR
WIDTH_A
16
PARAMETER_DEC
USR
WIDTH_B
16
PARAMETER_DEC
USR
WIDTH_RESULT
16
PARAMETER_DEC
USR
INPUT_REGISTER_A0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_ACLR_A0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A0
DATAA
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_A1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A1
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A2
DATAA
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_A3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_A3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_A3
DATAA
PARAMETER_UNKNOWN
DEF
REPRESENTATION_A
UNSIGNED
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
SIGNED_ACLR_A
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_PIPELINE_REGISTER_A
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_ACLR_A
ACLR0
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_B0
UNREGISTERED
PARAMETER_UNKNOWN
USR
INPUT_ACLR_B0
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B0
DATAB
PARAMETER_UNKNOWN
USR
INPUT_REGISTER_B1
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B1
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B1
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B2
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B2
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B2
DATAB
PARAMETER_UNKNOWN
DEF
INPUT_REGISTER_B3
CLOCK0
PARAMETER_UNKNOWN
DEF
INPUT_ACLR_B3
ACLR3
PARAMETER_UNKNOWN
DEF
INPUT_SOURCE_B3
DATAB
PARAMETER_UNKNOWN
DEF
REPRESENTATION_B
UNSIGNED
PARAMETER_UNKNOWN
USR
SIGNED_REGISTER_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
SIGNED_ACLR_B
ACLR3
PARAMETER_UNKNOWN
DEF
SIGNED_PIPELINE_REGISTER_B
CLOCK0
PARAMETER_UNKNOWN
USR
SIGNED_PIPELINE_ACLR_B
ACLR0
PARAMETER_UNKNOWN
USR
MULTIPLIER_REGISTER0
CLOCK0
PARAMETER_UNKNOWN
USR
MULTIPLIER_ACLR0
ACLR0
PARAMETER_UNKNOWN
USR
MULTIPLIER_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER1_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_REGISTER1
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_ACLR1
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1
CLOCK0
PARAMETER_UNKNOWN
USR
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1
ACLR0
PARAMETER_UNKNOWN
USR
MULTIPLIER_REGISTER2
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR2
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER3_DIRECTION
UNUSED
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3
ACLR3
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER01_SATURATION
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER23_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
MULTIPLIER23_SATURATION
NO
PARAMETER_UNKNOWN
DEF
ADDER1_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
ADDER3_ROUNDING
NO
PARAMETER_UNKNOWN
DEF
PORT_MULT0_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT1_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT2_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
PORT_MULT3_IS_SATURATED
UNUSED
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT01_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT01_SATURATION_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
MULT23_SATURATION_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB1_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_REGISTER
CLOCK0
PARAMETER_UNKNOWN
DEF
ADDNSUB3_ROUND_PIPELINE_ACLR
ACLR3
PARAMETER_UNKNOWN
DEF
PORT_SIGNA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SIGNB
PORT_UNUSED
PARAMETER_UNKNOWN
USR
OUTPUT_REGISTER
UNREGISTERED
PARAMETER_UNKNOWN
USR
OUTPUT_ACLR
ACLR0
PARAMETER_UNKNOWN
DEF
EXTRA_LATENCY
0
PARAMETER_UNKNOWN
DEF
DEDICATED_MULTIPLIER_CIRCUITRY
YES
PARAMETER_UNKNOWN
USR
DSP_BLOCK_BALANCING
AUTO
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
mult_add_6cr2
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
}
# used_port {
result
-1
3
datab
-1
3
dataa
-1
3
clock0
-1
3
aclr0
-1
3
ena0
-1
2
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|stratix_mac_mult.inc
37fae19b7be3fd367b8beebe8242bb70
..|..|..|altera|quartus60|libraries|megafunctions|stratix_mac_out.inc
7e6e79cdf4a1237186d7c89ebab37e
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2
}
# end
# entity
mult_add_6cr2
# storage
db|DE2_NIOS_DEVICE_LED.(112).cnf
db|DE2_NIOS_DEVICE_LED.(112).cnf
# case_insensitive
# source_file
db|mult_add_6cr2.tdf
ccedabb5c93b687771b2205bec2a480
6
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock0
-1
3
aclr0
-1
3
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_mult_cell:the_cpu_0_mult_cell|altmult_add:the_altmult_add_part_2|mult_add_6cr2:auto_generated
}
# end
# entity
altsyncram
# storage
db|DE2_NIOS_DEVICE_LED.(117).cnf
db|DE2_NIOS_DEVICE_LED.(117).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
8
PARAMETER_DEC
USR
NUMWORDS_B
256
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
4
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
cpu_0_ociram_default_contents.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_c572
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b
-1
3
q_a
-1
3
data_b
-1
3
data_a
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
byteena_a
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram
}
# end
# entity
altsyncram
# storage
db|DE2_NIOS_DEVICE_LED.(135).cnf
db|DE2_NIOS_DEVICE_LED.(135).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
36
PARAMETER_DEC
USR
WIDTHAD_A
7
PARAMETER_DEC
USR
NUMWORDS_A
128
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
36
PARAMETER_DEC
USR
WIDTHAD_B
7
PARAMETER_DEC
USR
NUMWORDS_B
128
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_e502
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b
-1
3
q_a
-1
3
data_b
-1
3
data_a
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram
}
# end
# entity
altsyncram_e502
# storage
db|DE2_NIOS_DEVICE_LED.(136).cnf
db|DE2_NIOS_DEVICE_LED.(136).cnf
# case_insensitive
# source_file
db|altsyncram_e502.tdf
9446da43b847e0ecd9b2232b5bac924
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a35
-1
3
q_a34
-1
3
q_a33
-1
3
q_a32
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b35
-1
3
data_b34
-1
3
data_b33
-1
3
data_b32
-1
3
data_b31
-1
3
data_b30
-1
3
data_b3
-1
3
data_b29
-1
3
data_b28
-1
3
data_b27
-1
3
data_b26
-1
3
data_b25
-1
3
data_b24
-1
3
data_b23
-1
3
data_b22
-1
3
data_b21
-1
3
data_b20
-1
3
data_b2
-1
3
data_b19
-1
3
data_b18
-1
3
data_b17
-1
3
data_b16
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a35
-1
3
data_a34
-1
3
data_a33
-1
3
data_a32
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_e502:auto_generated
}
# end
# entity
cpu_0_jtag_debug_module_wrapper
# storage
db|DE2_NIOS_DEVICE_LED.(137).cnf
db|DE2_NIOS_DEVICE_LED.(137).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0_jtag_debug_module_wrapper.v
58576f35f7afc18310b21278fcd75fb
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper
}
# end
# entity
cpu_0_jtag_debug_module
# storage
db|DE2_NIOS_DEVICE_LED.(138).cnf
db|DE2_NIOS_DEVICE_LED.(138).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0_jtag_debug_module.v
bec72e5dd05ae68576561fb83185889
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
SLD_NODE_INFO
286279168
PARAMETER_DEC
DEF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1
}
# end
# entity
epcs_controller
# storage
db|DE2_NIOS_DEVICE_LED.(140).cnf
db|DE2_NIOS_DEVICE_LED.(140).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
epcs_controller.v
c89accf9cc81943e676d7dd7db2923
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
epcs_controller_sub
# storage
db|DE2_NIOS_DEVICE_LED.(141).cnf
db|DE2_NIOS_DEVICE_LED.(141).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
epcs_controller.v
c89accf9cc81943e676d7dd7db2923
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
tornado_epcs_controller_atom
# storage
db|DE2_NIOS_DEVICE_LED.(142).cnf
db|DE2_NIOS_DEVICE_LED.(142).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
epcs_controller.v
c89accf9cc81943e676d7dd7db2923
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
altsyncram
# storage
db|DE2_NIOS_DEVICE_LED.(143).cnf
db|DE2_NIOS_DEVICE_LED.(143).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
7
PARAMETER_DEC
USR
NUMWORDS_A
128
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
epcs_controller_boot_rom.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_lo31
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a
-1
3
clock0
-1
3
address_a
-1
3
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# end
# entity
altsyncram_lo31
# storage
db|DE2_NIOS_DEVICE_LED.(144).cnf
db|DE2_NIOS_DEVICE_LED.(144).cnf
# case_insensitive
# source_file
db|altsyncram_lo31.tdf
9ddde324b51c04c89fa41c9a5fa2e2
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
epcs_controller_boot_rom.hex
d86d17f199903c5cf264c7b2416f745
}
# end
# entity
scfifo
# storage
db|DE2_NIOS_DEVICE_LED.(148).cnf
db|DE2_NIOS_DEVICE_LED.(148).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|scfifo.tdf
b67e14bc943b20b2659e8ef1077457
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
8
PARAMETER_DEC
USR
LPM_NUMWORDS
64
PARAMETER_DEC
USR
LPM_WIDTHU
6
PARAMETER_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
OFF
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
DEF
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_1n21
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw
-1
3
rdreq
-1
3
q
-1
3
full
-1
3
empty
-1
3
data
-1
3
clock
-1
3
aclr
-1
3
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
..|..|..|altera|quartus60|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
..|..|..|altera|quartus60|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
..|..|..|altera|quartus60|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
..|..|..|altera|quartus60|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo
}
# end
# entity
scfifo_1n21
# storage
db|DE2_NIOS_DEVICE_LED.(149).cnf
db|DE2_NIOS_DEVICE_LED.(149).cnf
# case_insensitive
# source_file
db|scfifo_1n21.tdf
d5fc7ef4ca6a77a9e6d2ed954fa7f9
6
# used_port {
wrreq
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated
}
# end
# entity
a_dpfifo_8t21
# storage
db|DE2_NIOS_DEVICE_LED.(150).cnf
db|DE2_NIOS_DEVICE_LED.(150).cnf
# case_insensitive
# source_file
db|a_dpfifo_8t21.tdf
68597cd6f8709a1f30ba8d18614bc1e
6
# used_port {
wreq
-1
3
usedw5
-1
3
usedw4
-1
3
usedw3
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo
}
# end
# entity
a_fefifo_7cf
# storage
db|DE2_NIOS_DEVICE_LED.(151).cnf
db|DE2_NIOS_DEVICE_LED.(151).cnf
# case_insensitive
# source_file
db|a_fefifo_7cf.tdf
e9b9bd5a3fbc2c9a111cf2c282067ae
6
# used_port {
wreq
-1
3
usedw_out5
-1
3
usedw_out4
-1
3
usedw_out3
-1
3
usedw_out2
-1
3
usedw_out1
-1
3
usedw_out0
-1
3
sclr
-1
3
rreq
-1
3
full
-1
3
empty
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state
}
# end
# entity
cntr_rj7
# storage
db|DE2_NIOS_DEVICE_LED.(152).cnf
db|DE2_NIOS_DEVICE_LED.(152).cnf
# case_insensitive
# source_file
db|cntr_rj7.tdf
e9ad20eb3a9ba0b48ce1adeb1c40fac9
6
# used_port {
updown
-1
3
sclr
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw
}
# end
# entity
dpram_5h21
# storage
db|DE2_NIOS_DEVICE_LED.(153).cnf
db|DE2_NIOS_DEVICE_LED.(153).cnf
# case_insensitive
# source_file
db|dpram_5h21.tdf
996e7efe2fc413754a7a58b245db56
6
# used_port {
wren
-1
3
wraddress5
-1
3
wraddress4
-1
3
wraddress3
-1
3
wraddress2
-1
3
wraddress1
-1
3
wraddress0
-1
3
rdaddress5
-1
3
rdaddress4
-1
3
rdaddress3
-1
3
rdaddress2
-1
3
rdaddress1
-1
3
rdaddress0
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclock
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram
}
# end
# entity
altsyncram_9tl1
# storage
db|DE2_NIOS_DEVICE_LED.(154).cnf
db|DE2_NIOS_DEVICE_LED.(154).cnf
# case_insensitive
# source_file
db|altsyncram_9tl1.tdf
2b5bfa2cceca02731b053491b4589b
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|dpram_5h21:FIFOram|altsyncram_9tl1:altsyncram2
}
# end
# entity
cntr_dl8
# storage
db|DE2_NIOS_DEVICE_LED.(155).cnf
db|DE2_NIOS_DEVICE_LED.(155).cnf
# case_insensitive
# source_file
db|cntr_dl8.tdf
42f7952a5af1ee7ea895bd41bbf82dca
6
# used_port {
sclr
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_dl8:rd_ptr_count
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_dl8:wr_ptr
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_dl8:rd_ptr_count
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|cntr_dl8:wr_ptr
}
# end
# entity
alt_jtag_atlantic
# storage
db|DE2_NIOS_DEVICE_LED.(157).cnf
db|DE2_NIOS_DEVICE_LED.(157).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|alt_jtag_atlantic.v
87ff42208e2dedfb02b115079ccac7e
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
INSTANCE_ID
0
PARAMETER_DEC
USR
SLD_NODE_INFO
00001100000000000110111000000000
PARAMETER_BIN
DEF
LOG2_TXFIFO_DEPTH
6
PARAMETER_DEC
USR
LOG2_RXFIFO_DEPTH
6
PARAMETER_DEC
USR
RESERVED
0
PARAMETER_DEC
DEF
DATA_WIDTH
8
PARAMETER_DEC
DEF
NODE_IR_WIDTH
1
PARAMETER_DEC
DEF
SCAN_LENGTH
11
PARAMETER_DEC
DEF
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic
}
# end
# entity
lcd_16207_0
# storage
db|DE2_NIOS_DEVICE_LED.(159).cnf
db|DE2_NIOS_DEVICE_LED.(159).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
lcd_16207_0.v
cde92621d6d0ba5e1205b3382258810
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
led_green
# storage
db|DE2_NIOS_DEVICE_LED.(161).cnf
db|DE2_NIOS_DEVICE_LED.(161).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
led_green.v
317aba1b6ec7c64905330e2809727b7
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
led_red
# storage
db|DE2_NIOS_DEVICE_LED.(163).cnf
db|DE2_NIOS_DEVICE_LED.(163).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
led_red.v
b7be12f5de8f39e91c3bc88b728e3c5a
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
sdram_0
# storage
db|DE2_NIOS_DEVICE_LED.(167).cnf
db|DE2_NIOS_DEVICE_LED.(167).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sdram_0.v
c0d8a4abac8ab1636331bc5e8065f2f0
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|sdram_0:the_sdram_0
}
# end
# entity
sdram_0_input_efifo_module
# storage
db|DE2_NIOS_DEVICE_LED.(168).cnf
db|DE2_NIOS_DEVICE_LED.(168).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sdram_0.v
c0d8a4abac8ab1636331bc5e8065f2f0
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module
}
# end
# entity
sram_0
# storage
db|DE2_NIOS_DEVICE_LED.(170).cnf
db|DE2_NIOS_DEVICE_LED.(170).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sram_0.v
c3b2eafff8bf07b985e8987d9dae44
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|sram_0:the_sram_0
}
# end
# entity
SRAM_16Bit_512K
# storage
db|DE2_NIOS_DEVICE_LED.(171).cnf
db|DE2_NIOS_DEVICE_LED.(171).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SRAM_16Bit_512K.v
5243bd2c4105c88d8dfa0c34457d75
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|sram_0:the_sram_0|SRAM_16Bit_512K:the_SRAM_16Bit_512K
}
# end
# entity
switch_pio
# storage
db|DE2_NIOS_DEVICE_LED.(173).cnf
db|DE2_NIOS_DEVICE_LED.(173).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
switch_pio.v
ed18b2a975bdc45a9795c3acbaa128
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
timer_0
# storage
db|DE2_NIOS_DEVICE_LED.(175).cnf
db|DE2_NIOS_DEVICE_LED.(175).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
timer_0.v
ccbb15c845a489eb6cc9a75c93a8f1ce
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|timer_0:the_timer_0
}
# end
# entity
timer_1
# storage
db|DE2_NIOS_DEVICE_LED.(177).cnf
db|DE2_NIOS_DEVICE_LED.(177).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
timer_1.v
fcf683d6bbb8b64a6fd44f47c07c86e1
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|timer_1:the_timer_1
}
# end
# entity
uart_0
# storage
db|DE2_NIOS_DEVICE_LED.(180).cnf
db|DE2_NIOS_DEVICE_LED.(180).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_0.v
615760767d8daf7aca756952e29836
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
uart_0_tx
# storage
db|DE2_NIOS_DEVICE_LED.(181).cnf
db|DE2_NIOS_DEVICE_LED.(181).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_0.v
615760767d8daf7aca756952e29836
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
uart_0_rx
# storage
db|DE2_NIOS_DEVICE_LED.(182).cnf
db|DE2_NIOS_DEVICE_LED.(182).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_0.v
615760767d8daf7aca756952e29836
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
uart_0_rx_stimulus_source
# storage
db|DE2_NIOS_DEVICE_LED.(183).cnf
db|DE2_NIOS_DEVICE_LED.(183).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_0.v
615760767d8daf7aca756952e29836
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
uart_0_regs
# storage
db|DE2_NIOS_DEVICE_LED.(184).cnf
db|DE2_NIOS_DEVICE_LED.(184).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
uart_0.v
615760767d8daf7aca756952e29836
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
I2C_AV_Config
# storage
db|DE2_NIOS_DEVICE_LED.(187).cnf
db|DE2_NIOS_DEVICE_LED.(187).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
I2C_AV_Config.v
7357e7a72a60488c27a21d6eca02
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
CLK_Freq
50000000
PARAMETER_DEC
DEF
I2C_Freq
20000
PARAMETER_DEC
DEF
LUT_SIZE
51
PARAMETER_DEC
DEF
Dummy_DATA
0
PARAMETER_DEC
DEF
SET_LIN_L
1
PARAMETER_DEC
DEF
SET_LIN_R
2
PARAMETER_DEC
DEF
SET_HEAD_L
3
PARAMETER_DEC
DEF
SET_HEAD_R
4
PARAMETER_DEC
DEF
A_PATH_CTRL
5
PARAMETER_DEC
DEF
D_PATH_CTRL
6
PARAMETER_DEC
DEF
POWER_ON
7
PARAMETER_DEC
DEF
SET_FORMAT
8
PARAMETER_DEC
DEF
SAMPLE_CTRL
9
PARAMETER_DEC
DEF
SET_ACTIVE
10
PARAMETER_DEC
DEF
SET_VIDEO
11
PARAMETER_DEC
DEF
}
# hierarchies {
I2C_AV_Config:u1
}
# end
# entity
I2C_Controller
# storage
db|DE2_NIOS_DEVICE_LED.(188).cnf
db|DE2_NIOS_DEVICE_LED.(188).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
I2C_Controller.v
f8e3f19243cbdb6ef4d39fe9182f8f3
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
I2C_AV_Config:u1|I2C_Controller:u0
}
# end
# entity
sld_hub
# storage
db|DE2_NIOS_DEVICE_LED.(189).cnf
db|DE2_NIOS_DEVICE_LED.(189).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|sld_hub.vhd
5510376c98712ae04829215cf7121b6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
3
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone II
PARAMETER_UNKNOWN
USR
n_nodes
2
PARAMETER_UNKNOWN
USR
n_sel_bits
2
PARAMETER_UNKNOWN
USR
n_node_ir_bits
5
PARAMETER_UNKNOWN
USR
node_info
0000110000000000011011100000000000010001000100000100011000000000
PARAMETER_BIN
USR
compilation_mode
0
PARAMETER_UNKNOWN
USR
}
# end
# entity
sld_jtag_state_machine
# storage
db|DE2_NIOS_DEVICE_LED.(190).cnf
db|DE2_NIOS_DEVICE_LED.(190).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|sld_hub.vhd
5510376c98712ae04829215cf7121b6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
ip_major_version
1
PARAMETER_DEC
USR
ip_minor_version
3
PARAMETER_DEC
USR
common_ip_version
0
PARAMETER_DEC
USR
 constraint(jtag_state)
15 downto 0
PARAMETER_STRING
USR
}
# end
# entity
lpm_shiftreg
# storage
db|DE2_NIOS_DEVICE_LED.(191).cnf
db|DE2_NIOS_DEVICE_LED.(191).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|lpm_shiftreg.tdf
5c3a6ccfa9758137252ac34dcc2420
6
# user_parameter {
LPM_WIDTH
10
PARAMETER_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
shiftin
-1
3
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
enable
-1
3
clock
-1
3
aclr
-1
3
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
..|..|..|altera|quartus60|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
}
# end
# entity
lpm_decode
# storage
db|DE2_NIOS_DEVICE_LED.(192).cnf
db|DE2_NIOS_DEVICE_LED.(192).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.tdf
2c635cd4e4aadce939ff33a1912efcc
6
# user_parameter {
LPM_WIDTH
3
PARAMETER_DEC
USR
LPM_DECODES
8
PARAMETER_DEC
USR
LPM_PIPELINE
1
PARAMETER_DEC
USR
CASCADE_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
decode_aoi
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
eq7
-1
3
eq3
-1
3
eq2
-1
3
eq1
-1
3
eq0
-1
3
enable
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
..|..|..|altera|quartus60|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
..|..|..|altera|quartus60|libraries|megafunctions|declut.inc
b1d5939399e5c04dfe1d209af8cc490
..|..|..|altera|quartus60|libraries|megafunctions|altshift.inc
70fa13aee7d6d160ef20b2de32813a
}
# end
# entity
decode_aoi
# storage
db|DE2_NIOS_DEVICE_LED.(193).cnf
db|DE2_NIOS_DEVICE_LED.(193).cnf
# case_insensitive
# source_file
db|decode_aoi.tdf
a84699e748e49ea893573fab224714be
6
# used_port {
eq7
-1
3
eq6
-1
3
eq5
-1
3
eq4
-1
3
eq3
-1
3
eq2
-1
3
eq1
-1
3
eq0
-1
3
enable
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# end
# entity
sld_dffex
# storage
db|DE2_NIOS_DEVICE_LED.(194).cnf
db|DE2_NIOS_DEVICE_LED.(194).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|sld_dffex.vhd
e07a659f3de75fb323a077607414df48
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
1
PARAMETER_DEC
USR
 constraint(d)
0 downto 0
PARAMETER_STRING
USR
 constraint(q)
0 downto 0
PARAMETER_STRING
USR
}
# end
# entity
sld_dffex
# storage
db|DE2_NIOS_DEVICE_LED.(195).cnf
db|DE2_NIOS_DEVICE_LED.(195).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|sld_dffex.vhd
e07a659f3de75fb323a077607414df48
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
7
PARAMETER_DEC
USR
 constraint(d)
6 downto 0
PARAMETER_STRING
USR
 constraint(q)
6 downto 0
PARAMETER_STRING
USR
}
# end
# entity
sld_dffex
# storage
db|DE2_NIOS_DEVICE_LED.(196).cnf
db|DE2_NIOS_DEVICE_LED.(196).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|sld_dffex.vhd
e07a659f3de75fb323a077607414df48
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
5
PARAMETER_DEC
USR
 constraint(d)
4 downto 0
PARAMETER_STRING
USR
 constraint(q)
4 downto 0
PARAMETER_STRING
USR
}
# end
# entity
sld_dffex
# storage
db|DE2_NIOS_DEVICE_LED.(197).cnf
db|DE2_NIOS_DEVICE_LED.(197).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|sld_dffex.vhd
e07a659f3de75fb323a077607414df48
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
2
PARAMETER_DEC
USR
 constraint(d)
1 downto 0
PARAMETER_STRING
USR
 constraint(q)
1 downto 0
PARAMETER_STRING
USR
}
# end
# entity
sld_rom_sr
# storage
db|DE2_NIOS_DEVICE_LED.(198).cnf
db|DE2_NIOS_DEVICE_LED.(198).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|sld_rom_sr.vhd
e685b197d41e27ef5fe9d8f6d2755ee3
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
96
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
 constraint(rom_data)
95 downto 0
PARAMETER_STRING
USR
}
# end
# entity
altsyncram
# storage
db|DE2_NIOS_DEVICE_LED.(199).cnf
db|DE2_NIOS_DEVICE_LED.(199).cnf
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
16
PARAMETER_UNKNOWN
USR
WIDTHAD_A
6
PARAMETER_UNKNOWN
USR
NUMWORDS_A
64
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
DE2_NIOS_DEVICE_LED0.rtl.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_mj01
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clocken0
-1
3
clock0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
..|..|..|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|..|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|..|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|..|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|..|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|..|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|..|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|..|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# end
# entity
altsyncram_mj01
# storage
db|DE2_NIOS_DEVICE_LED.(200).cnf
db|DE2_NIOS_DEVICE_LED.(200).cnf
# case_insensitive
# source_file
db|altsyncram_mj01.tdf
71949d3b091ffbb4ee648bac44547
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clocken0
-1
3
clock0
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
DE2_NIOS_DEVICE_LED0.rtl.mif
ac4ce8cf15e17b5e6d6691904e714e27
}
# end
# entity
DE2_NIOS_DEVICE_LED
# storage
db|DE2_NIOS_DEVICE_LED.(0).cnf
db|DE2_NIOS_DEVICE_LED.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
DE2_NIOS_DEVICE_LED.v
925fdf188943fcdebc1fba1402ae76
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
system_0
# storage
db|DE2_NIOS_DEVICE_LED.(6).cnf
db|DE2_NIOS_DEVICE_LED.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0
}
# end
# entity
button_pio_s1_arbitrator
# storage
db|DE2_NIOS_DEVICE_LED.(7).cnf
db|DE2_NIOS_DEVICE_LED.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|button_pio_s1_arbitrator:the_button_pio_s1
}
# end
# entity
clock_0_in_arbitrator
# storage
db|DE2_NIOS_DEVICE_LED.(24).cnf
db|DE2_NIOS_DEVICE_LED.(24).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_0_in_arbitrator:the_clock_0_in
}
# end
# entity
clock_0_out_arbitrator
# storage
db|DE2_NIOS_DEVICE_LED.(27).cnf
db|DE2_NIOS_DEVICE_LED.(27).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_0_out_arbitrator:the_clock_0_out
}
# end
# entity
clock_1_in_arbitrator
# storage
db|DE2_NIOS_DEVICE_LED.(28).cnf
db|DE2_NIOS_DEVICE_LED.(28).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_1_in_arbitrator:the_clock_1_in
}
# end
# entity
clock_1_out_arbitrator
# storage
db|DE2_NIOS_DEVICE_LED.(31).cnf
db|DE2_NIOS_DEVICE_LED.(31).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|clock_1_out_arbitrator:the_clock_1_out
}
# end
# entity
cpu_0_jtag_debug_module_arbitrator
# storage
db|DE2_NIOS_DEVICE_LED.(33).cnf
db|DE2_NIOS_DEVICE_LED.(33).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module
}
# end
# entity
cpu_0_data_master_arbitrator
# storage
db|DE2_NIOS_DEVICE_LED.(35).cnf
db|DE2_NIOS_DEVICE_LED.(35).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master
}
# end
# entity
cpu_0_instruction_master_arbitrator
# storage
db|DE2_NIOS_DEVICE_LED.(37).cnf
db|DE2_NIOS_DEVICE_LED.(37).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master
}
# end
# entity
cpu_0
# storage
db|DE2_NIOS_DEVICE_LED.(41).cnf
db|DE2_NIOS_DEVICE_LED.(41).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0
}
# end
# entity
cpu_0_ic_data_module
# storage
db|DE2_NIOS_DEVICE_LED.(54).cnf
db|DE2_NIOS_DEVICE_LED.(54).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
UNUSED
PARAMETER_STRING
DEF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_data_module:cpu_0_ic_data
}
# end
# entity
cpu_0_ic_tag_module
# storage
db|DE2_NIOS_DEVICE_LED.(56).cnf
db|DE2_NIOS_DEVICE_LED.(56).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
cpu_0_ic_tag_ram.mif
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_ic_tag_module:cpu_0_ic_tag
}
# end
# entity
cpu_0_bht_module
# storage
db|DE2_NIOS_DEVICE_LED.(57).cnf
db|DE2_NIOS_DEVICE_LED.(57).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
cpu_0_bht_ram.mif
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_bht_module:cpu_0_bht
}
# end
# entity
cpu_0_register_bank_a_module
# storage
db|DE2_NIOS_DEVICE_LED.(67).cnf
db|DE2_NIOS_DEVICE_LED.(67).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
cpu_0_rf_ram_a.mif
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_a_module:cpu_0_register_bank_a
}
# end
# entity
cpu_0_register_bank_b_module
# storage
db|DE2_NIOS_DEVICE_LED.(68).cnf
db|DE2_NIOS_DEVICE_LED.(68).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
cpu_0_rf_ram_b.mif
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_register_bank_b_module:cpu_0_register_bank_b
}
# end
# entity
cpu_0_dc_tag_module
# storage
db|DE2_NIOS_DEVICE_LED.(78).cnf
db|DE2_NIOS_DEVICE_LED.(78).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
cpu_0_dc_tag_ram.mif
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_tag_module:cpu_0_dc_tag
}
# end
# entity
cpu_0_dc_data_module
# storage
db|DE2_NIOS_DEVICE_LED.(79).cnf
db|DE2_NIOS_DEVICE_LED.(79).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
UNUSED
PARAMETER_STRING
DEF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_dc_data_module:cpu_0_dc_data
}
# end
# entity
cpu_0_nios2_oci
# storage
db|DE2_NIOS_DEVICE_LED.(80).cnf
db|DE2_NIOS_DEVICE_LED.(80).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci
}
# end
# entity
cpu_0_nios2_oci_debug
# storage
db|DE2_NIOS_DEVICE_LED.(81).cnf
db|DE2_NIOS_DEVICE_LED.(81).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug
}
# end
# entity
cpu_0_nios2_ocimem
# storage
db|DE2_NIOS_DEVICE_LED.(83).cnf
db|DE2_NIOS_DEVICE_LED.(83).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem
}
# end
# entity
cpu_0_ociram_lpm_dram_bdp_component_module
# storage
db|DE2_NIOS_DEVICE_LED.(87).cnf
db|DE2_NIOS_DEVICE_LED.(87).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
cpu_0_ociram_default_contents.mif
PARAMETER_STRING
USR
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component
}
# end
# entity
altsyncram_c572
# storage
db|DE2_NIOS_DEVICE_LED.(90).cnf
db|DE2_NIOS_DEVICE_LED.(90).cnf
# case_insensitive
# source_file
db|altsyncram_c572.tdf
50f68ec7be9838417778f637c130ad5
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_b
-1
3
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1
3
q_b16
-1
3
q_b15
-1
3
q_b14
-1
3
q_b13
-1
3
q_b12
-1
3
q_b11
-1
3
q_b10
-1
3
q_b1
-1
3
q_b0
-1
3
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a31
-1
3
q_a30
-1
3
q_a3
-1
3
q_a29
-1
3
q_a28
-1
3
q_a27
-1
3
q_a26
-1
3
q_a25
-1
3
q_a24
-1
3
q_a23
-1
3
q_a22
-1
3
q_a21
-1
3
q_a20
-1
3
q_a2
-1
3
q_a19
-1
3
q_a18
-1
3
q_a17
-1
3
q_a16
-1
3
q_a15
-1
3
q_a14
-1
3
q_a13
-1
3
q_a12
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
data_b9
-1
3
data_b8
-1
3
data_b7
-1
3
data_b6
-1
3
data_b5
-1
3
data_b4
-1
3
data_b31
-1
3
data_b30
-1
3
data_b3
-1
3
data_b29
-1
3
data_b28
-1
3
data_b27
-1
3
data_b26
-1
3
data_b25
-1
3
data_b24
-1
3
data_b23
-1
3
data_b22
-1
3
data_b21
-1
3
data_b20
-1
3
data_b2
-1
3
data_b19
-1
3
data_b18
-1
3
data_b17
-1
3
data_b16
-1
3
data_b15
-1
3
data_b14
-1
3
data_b13
-1
3
data_b12
-1
3
data_b11
-1
3
data_b10
-1
3
data_b1
-1
3
data_b0
-1
3
data_a9
-1
3
data_a8
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a31
-1
3
data_a30
-1
3
data_a3
-1
3
data_a29
-1
3
data_a28
-1
3
data_a27
-1
3
data_a26
-1
3
data_a25
-1
3
data_a24
-1
3
data_a23
-1
3
data_a22
-1
3
data_a21
-1
3
data_a20
-1
3
data_a2
-1
3
data_a19
-1
3
data_a18
-1
3
data_a17
-1
3
data_a16
-1
3
data_a15
-1
3
data_a14
-1
3
data_a13
-1
3
data_a12
-1
3
data_a11
-1
3
data_a10
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
byteena_a3
-1
3
byteena_a2
-1
3
byteena_a1
-1
3
byteena_a0
-1
3
address_b7
-1
3
address_b6
-1
3
address_b5
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
cpu_0_ociram_default_contents.mif
4a185aca18f84f8abbcc99dd99572f2
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_ocimem:the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component_module:cpu_0_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_c572:auto_generated
}
# end
# entity
cpu_0_nios2_avalon_reg
# storage
db|DE2_NIOS_DEVICE_LED.(94).cnf
db|DE2_NIOS_DEVICE_LED.(94).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_avalon_reg:the_cpu_0_nios2_avalon_reg
}
# end
# entity
cpu_0_nios2_oci_break
# storage
db|DE2_NIOS_DEVICE_LED.(97).cnf
db|DE2_NIOS_DEVICE_LED.(97).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_break:the_cpu_0_nios2_oci_break
}
# end
# entity
cpu_0_nios2_oci_xbrk
# storage
db|DE2_NIOS_DEVICE_LED.(100).cnf
db|DE2_NIOS_DEVICE_LED.(100).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_xbrk:the_cpu_0_nios2_oci_xbrk
}
# end
# entity
cpu_0_nios2_oci_dbrk
# storage
db|DE2_NIOS_DEVICE_LED.(103).cnf
db|DE2_NIOS_DEVICE_LED.(103).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk
}
# end
# entity
cpu_0_nios2_oci_match_paired
# storage
db|DE2_NIOS_DEVICE_LED.(113).cnf
db|DE2_NIOS_DEVICE_LED.(113).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_paired:cpu_0_nios2_oci_dbrk_hit0_match_paired
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_paired:cpu_0_nios2_oci_dbrk_hit2_match_paired
}
# end
# entity
cpu_0_nios2_oci_match_single
# storage
db|DE2_NIOS_DEVICE_LED.(114).cnf
db|DE2_NIOS_DEVICE_LED.(114).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit0_match_single
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit1_match_single
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit2_match_single
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dbrk:the_cpu_0_nios2_oci_dbrk|cpu_0_nios2_oci_match_single:cpu_0_nios2_oci_dbrk_hit3_match_single
}
# end
# entity
cpu_0_nios2_oci_itrace
# storage
db|DE2_NIOS_DEVICE_LED.(115).cnf
db|DE2_NIOS_DEVICE_LED.(115).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_itrace:the_cpu_0_nios2_oci_itrace
}
# end
# entity
cpu_0_nios2_oci_dtrace
# storage
db|DE2_NIOS_DEVICE_LED.(116).cnf
db|DE2_NIOS_DEVICE_LED.(116).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace
}
# end
# entity
cpu_0_nios2_oci_td_mode
# storage
db|DE2_NIOS_DEVICE_LED.(118).cnf
db|DE2_NIOS_DEVICE_LED.(118).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_dtrace:the_cpu_0_nios2_oci_dtrace|cpu_0_nios2_oci_td_mode:cpu_0_nios2_oci_trc_ctrl_td_mode
}
# end
# entity
cpu_0_nios2_oci_fifo
# storage
db|DE2_NIOS_DEVICE_LED.(119).cnf
db|DE2_NIOS_DEVICE_LED.(119).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo
}
# end
# entity
cpu_0_nios2_oci_compute_tm_count
# storage
db|DE2_NIOS_DEVICE_LED.(120).cnf
db|DE2_NIOS_DEVICE_LED.(120).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_compute_tm_count:cpu_0_nios2_oci_compute_tm_count_tm_count
}
# end
# entity
cpu_0_nios2_oci_fifowp_inc
# storage
db|DE2_NIOS_DEVICE_LED.(121).cnf
db|DE2_NIOS_DEVICE_LED.(121).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifowp_inc:cpu_0_nios2_oci_fifowp_inc_fifowp
}
# end
# entity
cpu_0_nios2_oci_fifocount_inc
# storage
db|DE2_NIOS_DEVICE_LED.(122).cnf
db|DE2_NIOS_DEVICE_LED.(122).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_fifo:the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifocount_inc:cpu_0_nios2_oci_fifocount_inc_fifocount
}
# end
# entity
cpu_0_nios2_oci_pib
# storage
db|DE2_NIOS_DEVICE_LED.(123).cnf
db|DE2_NIOS_DEVICE_LED.(123).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_pib:the_cpu_0_nios2_oci_pib
}
# end
# entity
cpu_0_nios2_oci_im
# storage
db|DE2_NIOS_DEVICE_LED.(124).cnf
db|DE2_NIOS_DEVICE_LED.(124).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im
}
# end
# entity
cpu_0_traceram_lpm_dram_bdp_component_module
# storage
db|DE2_NIOS_DEVICE_LED.(125).cnf
db|DE2_NIOS_DEVICE_LED.(125).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cpu_0.v
8c31e72c7a20937364c9be1a54fb0ba
7
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
lpm_file
UNUSED
PARAMETER_STRING
DEF
}
# hierarchies {
system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_im:the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component_module:cpu_0_traceram_lpm_dram_bdp_component
}
# end
# entity
jtag_uart_0_avalon_jtag_slave_arbitrator
# storage
db|DE2_NIOS_DEVICE_LED.(126).cnf
db|DE2_NIOS_DEVICE_LED.(126).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|jtag_uart_0_avalon_jtag_slave_arbitrator:the_jtag_uart_0_avalon_jtag_slave
}
# end
# entity
jtag_uart_0
# storage
db|DE2_NIOS_DEVICE_LED.(127).cnf
db|DE2_NIOS_DEVICE_LED.(127).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart_0.v
c6a0609371e45ee1a8fb83b9477d587
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0
}
# end
# entity
jtag_uart_0_scfifo_w
# storage
db|DE2_NIOS_DEVICE_LED.(128).cnf
db|DE2_NIOS_DEVICE_LED.(128).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart_0.v
c6a0609371e45ee1a8fb83b9477d587
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w
}
# end
# entity
jtag_uart_0_scfifo_r
# storage
db|DE2_NIOS_DEVICE_LED.(129).cnf
db|DE2_NIOS_DEVICE_LED.(129).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart_0.v
c6a0609371e45ee1a8fb83b9477d587
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r
}
# end
# entity
sdram_0_s1_arbitrator
# storage
db|DE2_NIOS_DEVICE_LED.(130).cnf
db|DE2_NIOS_DEVICE_LED.(130).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1
}
# end
# entity
rdv_fifo_for_clock_0_out_to_sdram_0_s1_module
# storage
db|DE2_NIOS_DEVICE_LED.(131).cnf
db|DE2_NIOS_DEVICE_LED.(131).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_0_out_to_sdram_0_s1_module:rdv_fifo_for_clock_0_out_to_sdram_0_s1
}
# end
# entity
rdv_fifo_for_clock_1_out_to_sdram_0_s1_module
# storage
db|DE2_NIOS_DEVICE_LED.(132).cnf
db|DE2_NIOS_DEVICE_LED.(132).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|sdram_0_s1_arbitrator:the_sdram_0_s1|rdv_fifo_for_clock_1_out_to_sdram_0_s1_module:rdv_fifo_for_clock_1_out_to_sdram_0_s1
}
# end
# entity
sram_0_avalon_slave_0_arbitrator
# storage
db|DE2_NIOS_DEVICE_LED.(133).cnf
db|DE2_NIOS_DEVICE_LED.(133).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0
}
# end
# entity
timer_0_s1_arbitrator
# storage
db|DE2_NIOS_DEVICE_LED.(134).cnf
db|DE2_NIOS_DEVICE_LED.(134).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|timer_0_s1_arbitrator:the_timer_0_s1
}
# end
# entity
timer_1_s1_arbitrator
# storage
db|DE2_NIOS_DEVICE_LED.(139).cnf
db|DE2_NIOS_DEVICE_LED.(139).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|timer_1_s1_arbitrator:the_timer_1_s1
}
# end
# entity
tri_state_bridge_0_avalon_slave_arbitrator
# storage
db|DE2_NIOS_DEVICE_LED.(145).cnf
db|DE2_NIOS_DEVICE_LED.(145).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave
}
# end
# entity
system_0_reset_clk_domain_synch_module
# storage
db|DE2_NIOS_DEVICE_LED.(146).cnf
db|DE2_NIOS_DEVICE_LED.(146).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch
}
# end
# entity
system_0_reset_clk_50_domain_synch_module
# storage
db|DE2_NIOS_DEVICE_LED.(147).cnf
db|DE2_NIOS_DEVICE_LED.(147).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
system_0.v
e3136d177f9ed7a558f1c65fa74ae29
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch
}
# end
# entity
pzdyqx
# storage
db|DE2_NIOS_DEVICE_LED.(156).cnf
db|DE2_NIOS_DEVICE_LED.(156).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|pzdyqx.vhd
d85a4c8b123947b430525d2326c5b3
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
pzdyqx0
8
PARAMETER_UNKNOWN
USR
pzdyqx9
1
PARAMETER_DEC
DEF
sld_node_info
552448
PARAMETER_DEC
DEF
pzdyqx5
1
PARAMETER_UNKNOWN
USR
pzdyqx6
01101010111101110000000010100010
PARAMETER_UNKNOWN
USR
pzdyqx1
3600
PARAMETER_UNKNOWN
USR
pzdyqx3
12
PARAMETER_UNKNOWN
USR
pzdyqx2
0
PARAMETER_UNKNOWN
USR
pzdyqx4
1
PARAMETER_UNKNOWN
USR
}
# end
# entity
MDCK2395
# storage
db|DE2_NIOS_DEVICE_LED.(158).cnf
db|DE2_NIOS_DEVICE_LED.(158).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|pzdyqx.vhd
d85a4c8b123947b430525d2326c5b3
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
osc_stages
13
PARAMETER_DEC
USR
osc_prescaler
8
PARAMETER_DEC
USR
clk_gen_width
27
PARAMETER_DEC
USR
}
# end
# entity
CJQJ5354
# storage
db|DE2_NIOS_DEVICE_LED.(160).cnf
db|DE2_NIOS_DEVICE_LED.(160).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|pzdyqx.vhd
d85a4c8b123947b430525d2326c5b3
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
width
19
PARAMETER_DEC
USR
modulus
0
PARAMETER_DEC
USR
 constraint(kvqq4224)
18 downto 0
PARAMETER_STRING
USR
}
# end
# entity
CJQJ5354
# storage
db|DE2_NIOS_DEVICE_LED.(162).cnf
db|DE2_NIOS_DEVICE_LED.(162).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|pzdyqx.vhd
d85a4c8b123947b430525d2326c5b3
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
width
12
PARAMETER_DEC
USR
modulus
3600
PARAMETER_DEC
USR
 constraint(kvqq4224)
11 downto 0
PARAMETER_STRING
USR
}
# end
# entity
PZMU7345
# storage
db|DE2_NIOS_DEVICE_LED.(164).cnf
db|DE2_NIOS_DEVICE_LED.(164).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|pzdyqx.vhd
d85a4c8b123947b430525d2326c5b3
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
width
13
PARAMETER_DEC
USR
 constraint(yjoq9945)
12 downto 0
PARAMETER_STRING
USR
}
# end
# entity
VELJ8121
# storage
db|DE2_NIOS_DEVICE_LED.(165).cnf
db|DE2_NIOS_DEVICE_LED.(165).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|pzdyqx.vhd
d85a4c8b123947b430525d2326c5b3
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
n_bits
72
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
 constraint(gisa9786)
71 downto 0
PARAMETER_STRING
USR
}
# end
# entity
sld_hub
# storage
db|DE2_NIOS_DEVICE_LED.(166).cnf
db|DE2_NIOS_DEVICE_LED.(166).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|sld_hub.vhd
5510376c98712ae04829215cf7121b6
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
sld_hub_ip_version
1
PARAMETER_UNKNOWN
USR
sld_hub_ip_minor_version
3
PARAMETER_UNKNOWN
USR
sld_common_ip_version
0
PARAMETER_UNKNOWN
USR
device_family
Cyclone II
PARAMETER_UNKNOWN
USR
n_nodes
3
PARAMETER_UNKNOWN
USR
n_sel_bits
2
PARAMETER_UNKNOWN
USR
n_node_ir_bits
5
PARAMETER_UNKNOWN
USR
node_info
000000000000100001101110000000000000110000000000011011100000000000010001000100000100011000000000
PARAMETER_BIN
USR
compilation_mode
0
PARAMETER_UNKNOWN
USR
}
# end
# entity
sld_dffex
# storage
db|DE2_NIOS_DEVICE_LED.(169).cnf
db|DE2_NIOS_DEVICE_LED.(169).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|sld_dffex.vhd
e07a659f3de75fb323a077607414df48
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
size
3
PARAMETER_DEC
USR
 constraint(d)
2 downto 0
PARAMETER_STRING
USR
 constraint(q)
2 downto 0
PARAMETER_STRING
USR
}
# end
# entity
sld_rom_sr
# storage
db|DE2_NIOS_DEVICE_LED.(172).cnf
db|DE2_NIOS_DEVICE_LED.(172).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
..|..|..|altera|quartus60|libraries|megafunctions|sld_rom_sr.vhd
e685b197d41e27ef5fe9d8f6d2755ee3
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
common_ip_version
0
PARAMETER_DEC
USR
n_bits
128
PARAMETER_DEC
USR
word_size
4
PARAMETER_DEC
USR
 constraint(rom_data)
127 downto 0
PARAMETER_STRING
USR
}
# end
# complete

