{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 08 00:55:33 2007 " "Info: Processing started: Sun Apr 08 00:55:33 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off DE2_NIOS_DEVICE_LED -c DE2_NIOS_DEVICE_LED --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DE2_NIOS_DEVICE_LED -c DE2_NIOS_DEVICE_LED --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updateir~7 " "Warning: Node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updateir~7\" is a latch" {  } { { "cpu_0_jtag_debug_module.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0_jtag_debug_module.v" 141 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updatedr~8 " "Warning: Node \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updatedr~8\" is a latch" {  } { { "cpu_0_jtag_debug_module.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0_jtag_debug_module.v" 140 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "altera_internal_jtag~UPDATEUSER " "Info: Assuming node \"altera_internal_jtag~UPDATEUSER\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } {  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_CLOCK_SETTING_NOT_USED" "CLOCK_27 " "Warning: Clock Setting \"CLOCK_27\" is unassigned" {  } {  } 0 0 "Clock Setting \"%1!s!\" is unassigned" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "I2C_AV_Config:u1\|mI2C_CTRL_CLK " "Info: Detected ripple clock \"I2C_AV_Config:u1\|mI2C_CTRL_CLK\" as buffer" {  } { { "I2C_AV_Config.v" "" { Text "C:/csce496/final_project/PROCESSOR/I2C_AV_Config.v" 16 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u1\|mI2C_CTRL_CLK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk0 " "Info: No valid register-to-register data paths exist for clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk0\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 register system_0:u0\|cpu_0:the_cpu_0\|d_address\[23\] register system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_8_reg_segment_2\[6\] 526 ps " "Info: Slack time is 526 ps for clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" between source register \"system_0:u0\|cpu_0:the_cpu_0\|d_address\[23\]\" and destination register \"system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_8_reg_segment_2\[6\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "105.55 MHz 9.474 ns " "Info: Fmax is 105.55 MHz (period= 9.474 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.803 ns + Largest register register " "Info: + Largest register to register requirement is 9.803 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 7.642 ns " "Info: + Latch edge is 7.642 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 10.000 ns -2.358 ns  50 " "Info: Clock period of Destination clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" is 10.000 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.358 ns " "Info: - Launch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 10.000 ns -2.358 ns  50 " "Info: Clock period of Source clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" is 10.000 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.017 ns + Largest " "Info: + Largest clock skew is 0.017 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 destination 2.649 ns + Shortest register " "Info: + Shortest clock path from clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" to destination register is 2.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G3 3158 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 3158; COMB Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.091 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.537 ns) 2.649 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_8_reg_segment_2\[6\] 3 REG LCFF_X23_Y13_N13 1 " "Info: 3: + IC(1.021 ns) + CELL(0.537 ns) = 2.649 ns; Loc. = LCFF_X23_Y13_N13; Fanout = 1; REG Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_8_reg_segment_2\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.558 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 1932 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.27 % ) " "Info: Total cell delay = 0.537 ns ( 20.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.112 ns ( 79.73 % ) " "Info: Total interconnect delay = 2.112 ns ( 79.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.649 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.649 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } { 0.000ns 1.091ns 1.021ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 source 2.632 ns - Longest register " "Info: - Longest clock path from clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" to source register is 2.632 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G3 3158 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 3158; COMB Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.091 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.004 ns) + CELL(0.537 ns) 2.632 ns system_0:u0\|cpu_0:the_cpu_0\|d_address\[23\] 3 REG LCFF_X21_Y11_N15 5 " "Info: 3: + IC(1.004 ns) + CELL(0.537 ns) = 2.632 ns; Loc. = LCFF_X21_Y11_N15; Fanout = 5; REG Node = 'system_0:u0\|cpu_0:the_cpu_0\|d_address\[23\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.541 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_address[23] } "NODE_NAME" } } { "cpu_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0.v" 8484 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.40 % ) " "Info: Total cell delay = 0.537 ns ( 20.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.095 ns ( 79.60 % ) " "Info: Total interconnect delay = 2.095 ns ( 79.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.632 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_address[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.632 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_address[23] } { 0.000ns 1.091ns 1.004ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.649 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.649 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } { 0.000ns 1.091ns 1.021ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.632 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_address[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.632 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_address[23] } { 0.000ns 1.091ns 1.004ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "cpu_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0.v" 8484 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" {  } { { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 1932 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.649 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.649 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } { 0.000ns 1.091ns 1.021ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.632 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_address[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.632 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_address[23] } { 0.000ns 1.091ns 1.004ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.277 ns - Longest register register " "Info: - Longest register to register delay is 9.277 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns system_0:u0\|cpu_0:the_cpu_0\|d_address\[23\] 1 REG LCFF_X21_Y11_N15 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y11_N15; Fanout = 5; REG Node = 'system_0:u0\|cpu_0:the_cpu_0\|d_address\[23\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|d_address[23] } "NODE_NAME" } } { "cpu_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0.v" 8484 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.960 ns) + CELL(0.371 ns) 2.331 ns system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|cpu_0_data_master_requests_cfi_flash_0_s1 2 COMB LCCOMB_X21_Y11_N10 42 " "Info: 2: + IC(1.960 ns) + CELL(0.371 ns) = 2.331 ns; Loc. = LCCOMB_X21_Y11_N10; Fanout = 42; COMB Node = 'system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|cpu_0_data_master_requests_cfi_flash_0_s1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.331 ns" { system_0:u0|cpu_0:the_cpu_0|d_address[23] system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_requests_cfi_flash_0_s1 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 4642 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.289 ns) + CELL(0.150 ns) 3.770 ns system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|cpu_0_data_master_qualified_request_cfi_flash_0_s1~175 3 COMB LCCOMB_X20_Y12_N14 1 " "Info: 3: + IC(1.289 ns) + CELL(0.150 ns) = 3.770 ns; Loc. = LCCOMB_X20_Y12_N14; Fanout = 1; COMB Node = 'system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|cpu_0_data_master_qualified_request_cfi_flash_0_s1~175'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.439 ns" { system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_requests_cfi_flash_0_s1 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~175 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 4640 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.262 ns) + CELL(0.275 ns) 4.307 ns system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|cpu_0_data_master_qualified_request_cfi_flash_0_s1~176 4 COMB LCCOMB_X20_Y12_N4 12 " "Info: 4: + IC(0.262 ns) + CELL(0.275 ns) = 4.307 ns; Loc. = LCCOMB_X20_Y12_N4; Fanout = 12; COMB Node = 'system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|cpu_0_data_master_qualified_request_cfi_flash_0_s1~176'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.537 ns" { system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~175 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~176 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 4640 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.286 ns) + CELL(0.275 ns) 4.868 ns system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|tri_state_bridge_0_avalon_slave_grant_vector\[1\]~31 5 COMB LCCOMB_X20_Y12_N26 33 " "Info: 5: + IC(0.286 ns) + CELL(0.275 ns) = 4.868 ns; Loc. = LCCOMB_X20_Y12_N26; Fanout = 33; COMB Node = 'system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|tri_state_bridge_0_avalon_slave_grant_vector\[1\]~31'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.561 ns" { system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~176 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[1]~31 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 4750 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.784 ns) + CELL(0.150 ns) 5.802 ns system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|in_a_write_cycle~16 6 COMB LCCOMB_X20_Y8_N2 10 " "Info: 6: + IC(0.784 ns) + CELL(0.150 ns) = 5.802 ns; Loc. = LCCOMB_X20_Y8_N2; Fanout = 10; COMB Node = 'system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|in_a_write_cycle~16'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.934 ns" { system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[1]~31 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|in_a_write_cycle~16 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 4710 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.964 ns) + CELL(0.271 ns) 7.037 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_count_enable~595 7 COMB LCCOMB_X24_Y9_N6 1 " "Info: 7: + IC(0.964 ns) + CELL(0.271 ns) = 7.037 ns; Loc. = LCCOMB_X24_Y9_N6; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_count_enable~595'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.235 ns" { system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|in_a_write_cycle~16 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~595 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 1730 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.242 ns) + CELL(0.150 ns) 7.429 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_count_enable~596 8 COMB LCCOMB_X24_Y9_N2 6 " "Info: 8: + IC(0.242 ns) + CELL(0.150 ns) = 7.429 ns; Loc. = LCCOMB_X24_Y9_N2; Fanout = 6; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_count_enable~596'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.392 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~595 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~596 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 1730 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.268 ns) + CELL(0.150 ns) 7.847 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|always7~18 9 COMB LCCOMB_X24_Y9_N14 8 " "Info: 9: + IC(0.268 ns) + CELL(0.150 ns) = 7.847 ns; Loc. = LCCOMB_X24_Y9_N14; Fanout = 8; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|always7~18'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.418 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~596 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~18 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.770 ns) + CELL(0.660 ns) 9.277 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_8_reg_segment_2\[6\] 10 REG LCFF_X23_Y13_N13 1 " "Info: 10: + IC(0.770 ns) + CELL(0.660 ns) = 9.277 ns; Loc. = LCFF_X23_Y13_N13; Fanout = 1; REG Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_8_reg_segment_2\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.430 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~18 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 1932 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.452 ns ( 26.43 % ) " "Info: Total cell delay = 2.452 ns ( 26.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.825 ns ( 73.57 % ) " "Info: Total interconnect delay = 6.825 ns ( 73.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.277 ns" { system_0:u0|cpu_0:the_cpu_0|d_address[23] system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_requests_cfi_flash_0_s1 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~175 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~176 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[1]~31 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|in_a_write_cycle~16 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~595 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~596 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~18 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.277 ns" { system_0:u0|cpu_0:the_cpu_0|d_address[23] system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_requests_cfi_flash_0_s1 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~175 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~176 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[1]~31 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|in_a_write_cycle~16 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~595 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~596 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~18 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } { 0.000ns 1.960ns 1.289ns 0.262ns 0.286ns 0.784ns 0.964ns 0.242ns 0.268ns 0.770ns } { 0.000ns 0.371ns 0.150ns 0.275ns 0.275ns 0.150ns 0.271ns 0.150ns 0.150ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.649 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.649 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } { 0.000ns 1.091ns 1.021ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.632 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_address[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.632 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_address[23] } { 0.000ns 1.091ns 1.004ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.277 ns" { system_0:u0|cpu_0:the_cpu_0|d_address[23] system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_requests_cfi_flash_0_s1 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~175 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~176 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[1]~31 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|in_a_write_cycle~16 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~595 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~596 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~18 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.277 ns" { system_0:u0|cpu_0:the_cpu_0|d_address[23] system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_requests_cfi_flash_0_s1 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~175 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~176 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[1]~31 system_0:u0|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|in_a_write_cycle~16 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~595 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~596 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~18 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } { 0.000ns 1.960ns 1.289ns 0.262ns 0.286ns 0.784ns 0.964ns 0.242ns 0.268ns 0.770ns } { 0.000ns 0.371ns 0.150ns 0.275ns 0.275ns 0.150ns 0.271ns 0.150ns 0.150ns 0.660ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLOCK_50 register system_0:u0\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|rd_address register system_0:u0\|sdram_0:the_sdram_0\|m_addr\[5\] 10.831 ns " "Info: Slack time is 10.831 ns for clock \"CLOCK_50\" between source register \"system_0:u0\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|rd_address\" and destination register \"system_0:u0\|sdram_0:the_sdram_0\|m_addr\[5\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "109.06 MHz 9.169 ns " "Info: Fmax is 109.06 MHz (period= 9.169 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.510 ns + Largest register register " "Info: + Largest register to register requirement is 19.510 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLOCK_50 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLOCK_50\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLOCK_50 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLOCK_50\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.164 ns + Largest " "Info: + Largest clock skew is -0.164 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.493 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 487 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 487; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.089 ns) + CELL(0.287 ns) 2.493 ns system_0:u0\|sdram_0:the_sdram_0\|m_addr\[5\] 3 REG IOC_X0_Y10_N2 1 " "Info: 3: + IC(1.089 ns) + CELL(0.287 ns) = 2.493 ns; Loc. = IOC_X0_Y10_N2; Fanout = 1; REG Node = 'system_0:u0\|sdram_0:the_sdram_0\|m_addr\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.376 ns" { CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|m_addr[5] } "NODE_NAME" } } { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 421 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.286 ns ( 51.58 % ) " "Info: Total cell delay = 1.286 ns ( 51.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.207 ns ( 48.42 % ) " "Info: Total interconnect delay = 1.207 ns ( 48.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.493 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|m_addr[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.493 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|m_addr[5] } { 0.000ns 0.000ns 0.118ns 1.089ns } { 0.000ns 0.999ns 0.000ns 0.287ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.657 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.657 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 487 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 487; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.003 ns) + CELL(0.537 ns) 2.657 ns system_0:u0\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|rd_address 3 REG LCFF_X5_Y9_N25 42 " "Info: 3: + IC(1.003 ns) + CELL(0.537 ns) = 2.657 ns; Loc. = LCFF_X5_Y9_N25; Fanout = 42; REG Node = 'system_0:u0\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|rd_address'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.540 ns" { CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address } "NODE_NAME" } } { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.81 % ) " "Info: Total cell delay = 1.536 ns ( 57.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.121 ns ( 42.19 % ) " "Info: Total interconnect delay = 1.121 ns ( 42.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.657 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.657 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address } { 0.000ns 0.000ns 0.118ns 1.003ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.493 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|m_addr[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.493 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|m_addr[5] } { 0.000ns 0.000ns 0.118ns 1.089ns } { 0.000ns 0.999ns 0.000ns 0.287ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.657 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.657 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address } { 0.000ns 0.000ns 0.118ns 1.003ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 56 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.076 ns - " "Info: - Micro setup delay of destination is 0.076 ns" {  } { { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 421 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.493 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|m_addr[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.493 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|m_addr[5] } { 0.000ns 0.000ns 0.118ns 1.089ns } { 0.000ns 0.999ns 0.000ns 0.287ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.657 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.657 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address } { 0.000ns 0.000ns 0.118ns 1.003ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.679 ns - Longest register register " "Info: - Longest register to register delay is 8.679 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns system_0:u0\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|rd_address 1 REG LCFF_X5_Y9_N25 42 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X5_Y9_N25; Fanout = 42; REG Node = 'system_0:u0\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|rd_address'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address } "NODE_NAME" } } { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.024 ns) + CELL(0.275 ns) 1.299 ns system_0:u0\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|rd_data\[27\]~426 2 COMB LCCOMB_X9_Y9_N30 2 " "Info: 2: + IC(1.024 ns) + CELL(0.275 ns) = 1.299 ns; Loc. = LCCOMB_X9_Y9_N30; Fanout = 2; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module\|rd_data\[27\]~426'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.299 ns" { system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_data[27]~426 } "NODE_NAME" } } { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.393 ns) 2.723 ns system_0:u0\|sdram_0:the_sdram_0\|pending~267 3 COMB LCCOMB_X9_Y9_N4 1 " "Info: 3: + IC(1.031 ns) + CELL(0.393 ns) = 2.723 ns; Loc. = LCCOMB_X9_Y9_N4; Fanout = 1; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|pending~267'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.424 ns" { system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_data[27]~426 system_0:u0|sdram_0:the_sdram_0|pending~267 } "NODE_NAME" } } { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 247 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.658 ns) + CELL(0.275 ns) 3.656 ns system_0:u0\|sdram_0:the_sdram_0\|pending~271 4 COMB LCCOMB_X7_Y9_N10 3 " "Info: 4: + IC(0.658 ns) + CELL(0.275 ns) = 3.656 ns; Loc. = LCCOMB_X7_Y9_N10; Fanout = 3; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|pending~271'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.933 ns" { system_0:u0|sdram_0:the_sdram_0|pending~267 system_0:u0|sdram_0:the_sdram_0|pending~271 } "NODE_NAME" } } { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 247 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.673 ns) + CELL(0.393 ns) 4.722 ns system_0:u0\|sdram_0:the_sdram_0\|Selector41~33 5 COMB LCCOMB_X5_Y9_N10 8 " "Info: 5: + IC(0.673 ns) + CELL(0.393 ns) = 4.722 ns; Loc. = LCCOMB_X5_Y9_N10; Fanout = 8; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|Selector41~33'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.066 ns" { system_0:u0|sdram_0:the_sdram_0|pending~271 system_0:u0|sdram_0:the_sdram_0|Selector41~33 } "NODE_NAME" } } { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 439 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.706 ns) + CELL(0.275 ns) 5.703 ns system_0:u0\|sdram_0:the_sdram_0\|Selector89~180 6 COMB LCCOMB_X8_Y9_N26 1 " "Info: 6: + IC(0.706 ns) + CELL(0.275 ns) = 5.703 ns; Loc. = LCCOMB_X8_Y9_N26; Fanout = 1; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|Selector89~180'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.981 ns" { system_0:u0|sdram_0:the_sdram_0|Selector41~33 system_0:u0|sdram_0:the_sdram_0|Selector89~180 } "NODE_NAME" } } { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 439 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.107 ns) + CELL(0.420 ns) 7.230 ns system_0:u0\|sdram_0:the_sdram_0\|Selector89~181 7 COMB LCCOMB_X8_Y9_N10 1 " "Info: 7: + IC(1.107 ns) + CELL(0.420 ns) = 7.230 ns; Loc. = LCCOMB_X8_Y9_N10; Fanout = 1; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|Selector89~181'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.527 ns" { system_0:u0|sdram_0:the_sdram_0|Selector89~180 system_0:u0|sdram_0:the_sdram_0|Selector89~181 } "NODE_NAME" } } { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 439 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.180 ns) + CELL(0.269 ns) 8.679 ns system_0:u0\|sdram_0:the_sdram_0\|m_addr\[5\] 8 REG IOC_X0_Y10_N2 1 " "Info: 8: + IC(1.180 ns) + CELL(0.269 ns) = 8.679 ns; Loc. = IOC_X0_Y10_N2; Fanout = 1; REG Node = 'system_0:u0\|sdram_0:the_sdram_0\|m_addr\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.449 ns" { system_0:u0|sdram_0:the_sdram_0|Selector89~181 system_0:u0|sdram_0:the_sdram_0|m_addr[5] } "NODE_NAME" } } { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 421 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.300 ns ( 26.50 % ) " "Info: Total cell delay = 2.300 ns ( 26.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.379 ns ( 73.50 % ) " "Info: Total interconnect delay = 6.379 ns ( 73.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.679 ns" { system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_data[27]~426 system_0:u0|sdram_0:the_sdram_0|pending~267 system_0:u0|sdram_0:the_sdram_0|pending~271 system_0:u0|sdram_0:the_sdram_0|Selector41~33 system_0:u0|sdram_0:the_sdram_0|Selector89~180 system_0:u0|sdram_0:the_sdram_0|Selector89~181 system_0:u0|sdram_0:the_sdram_0|m_addr[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.679 ns" { system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_data[27]~426 system_0:u0|sdram_0:the_sdram_0|pending~267 system_0:u0|sdram_0:the_sdram_0|pending~271 system_0:u0|sdram_0:the_sdram_0|Selector41~33 system_0:u0|sdram_0:the_sdram_0|Selector89~180 system_0:u0|sdram_0:the_sdram_0|Selector89~181 system_0:u0|sdram_0:the_sdram_0|m_addr[5] } { 0.000ns 1.024ns 1.031ns 0.658ns 0.673ns 0.706ns 1.107ns 1.180ns } { 0.000ns 0.275ns 0.393ns 0.275ns 0.393ns 0.275ns 0.420ns 0.269ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.493 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|m_addr[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.493 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|m_addr[5] } { 0.000ns 0.000ns 0.118ns 1.089ns } { 0.000ns 0.999ns 0.000ns 0.287ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.657 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.657 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address } { 0.000ns 0.000ns 0.118ns 1.003ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.679 ns" { system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_data[27]~426 system_0:u0|sdram_0:the_sdram_0|pending~267 system_0:u0|sdram_0:the_sdram_0|pending~271 system_0:u0|sdram_0:the_sdram_0|Selector41~33 system_0:u0|sdram_0:the_sdram_0|Selector89~180 system_0:u0|sdram_0:the_sdram_0|Selector89~181 system_0:u0|sdram_0:the_sdram_0|m_addr[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.679 ns" { system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_address system_0:u0|sdram_0:the_sdram_0|sdram_0_input_efifo_module:the_sdram_0_input_efifo_module|rd_data[27]~426 system_0:u0|sdram_0:the_sdram_0|pending~267 system_0:u0|sdram_0:the_sdram_0|pending~271 system_0:u0|sdram_0:the_sdram_0|Selector41~33 system_0:u0|sdram_0:the_sdram_0|Selector89~180 system_0:u0|sdram_0:the_sdram_0|Selector89~181 system_0:u0|sdram_0:the_sdram_0|m_addr[5] } { 0.000ns 1.024ns 1.031ns 0.658ns 0.673ns 0.706ns 1.107ns 1.180ns } { 0.000ns 0.275ns 0.393ns 0.275ns 0.393ns 0.275ns 0.420ns 0.269ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 register system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[11\] 139.55 MHz 7.166 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 139.55 MHz between source register \"sld_hub:sld_hub_inst\|jtag_debug_mode_usr1\" and destination register \"system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[11\]\" (period= 7.166 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.925 ns + Longest register register " "Info: + Longest register to register delay is 6.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LCFF_X35_Y16_N21 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y16_N21; Fanout = 15; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "../../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.105 ns) + CELL(0.398 ns) 1.503 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[35\]~4756 2 COMB LCCOMB_X34_Y14_N8 10 " "Info: 2: + IC(1.105 ns) + CELL(0.398 ns) = 1.503 ns; Loc. = LCCOMB_X34_Y14_N8; Fanout = 10; COMB Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[35\]~4756'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.503 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4756 } "NODE_NAME" } } { "cpu_0_jtag_debug_module.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0_jtag_debug_module.v" 222 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.753 ns) + CELL(0.420 ns) 2.676 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[12\]~4765 3 COMB LCCOMB_X34_Y11_N8 23 " "Info: 3: + IC(0.753 ns) + CELL(0.420 ns) = 2.676 ns; Loc. = LCCOMB_X34_Y11_N8; Fanout = 23; COMB Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[12\]~4765'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.173 ns" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4756 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12]~4765 } "NODE_NAME" } } { "cpu_0_jtag_debug_module.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0_jtag_debug_module.v" 222 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.088 ns) + CELL(0.271 ns) 5.035 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4838 4 COMB LCCOMB_X31_Y10_N6 1 " "Info: 4: + IC(2.088 ns) + CELL(0.271 ns) = 5.035 ns; Loc. = LCCOMB_X31_Y10_N6; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4838'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.359 ns" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12]~4765 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4838 } "NODE_NAME" } } { "cpu_0_jtag_debug_module.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0_jtag_debug_module.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.263 ns) + CELL(0.438 ns) 5.736 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4839 5 COMB LCCOMB_X31_Y10_N8 1 " "Info: 5: + IC(0.263 ns) + CELL(0.438 ns) = 5.736 ns; Loc. = LCCOMB_X31_Y10_N8; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4839'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.701 ns" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4838 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4839 } "NODE_NAME" } } { "cpu_0_jtag_debug_module.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0_jtag_debug_module.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.955 ns) + CELL(0.150 ns) 6.841 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4840 6 COMB LCCOMB_X34_Y11_N24 1 " "Info: 6: + IC(0.955 ns) + CELL(0.150 ns) = 6.841 ns; Loc. = LCCOMB_X34_Y11_N24; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr~4840'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.105 ns" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4839 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4840 } "NODE_NAME" } } { "cpu_0_jtag_debug_module.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0_jtag_debug_module.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.925 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[11\] 7 REG LCFF_X34_Y11_N25 2 " "Info: 7: + IC(0.000 ns) + CELL(0.084 ns) = 6.925 ns; Loc. = LCFF_X34_Y11_N25; Fanout = 2; REG Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[11\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4840 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[11] } "NODE_NAME" } } { "cpu_0_jtag_debug_module.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0_jtag_debug_module.v" 222 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.761 ns ( 25.43 % ) " "Info: Total cell delay = 1.761 ns ( 25.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.164 ns ( 74.57 % ) " "Info: Total interconnect delay = 5.164 ns ( 74.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.925 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4756 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12]~4765 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4838 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4839 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4840 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.925 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4756 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12]~4765 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4838 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4839 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4840 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[11] } { 0.000ns 1.105ns 0.753ns 2.088ns 0.263ns 0.955ns 0.000ns } { 0.000ns 0.398ns 0.420ns 0.271ns 0.438ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.027 ns - Smallest " "Info: - Smallest clock skew is -0.027 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.397 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.874 ns) + CELL(0.000 ns) 2.874 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 191 " "Info: 2: + IC(2.874 ns) + CELL(0.000 ns) = 2.874 ns; Loc. = CLKCTRL_G0; Fanout = 191; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.874 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.986 ns) + CELL(0.537 ns) 4.397 ns system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[11\] 3 REG LCFF_X34_Y11_N25 2 " "Info: 3: + IC(0.986 ns) + CELL(0.537 ns) = 4.397 ns; Loc. = LCFF_X34_Y11_N25; Fanout = 2; REG Node = 'system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|sr\[11\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.523 ns" { altera_internal_jtag~TCKUTAPclkctrl system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[11] } "NODE_NAME" } } { "cpu_0_jtag_debug_module.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0_jtag_debug_module.v" 222 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 12.21 % ) " "Info: Total cell delay = 0.537 ns ( 12.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.860 ns ( 87.79 % ) " "Info: Total interconnect delay = 3.860 ns ( 87.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.397 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.397 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[11] } { 0.000ns 2.874ns 0.986ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 4.424 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 4.424 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.874 ns) + CELL(0.000 ns) 2.874 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 191 " "Info: 2: + IC(2.874 ns) + CELL(0.000 ns) = 2.874 ns; Loc. = CLKCTRL_G0; Fanout = 191; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.874 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.013 ns) + CELL(0.537 ns) 4.424 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 3 REG LCFF_X35_Y16_N21 15 " "Info: 3: + IC(1.013 ns) + CELL(0.537 ns) = 4.424 ns; Loc. = LCFF_X35_Y16_N21; Fanout = 15; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.550 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "../../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 12.14 % ) " "Info: Total cell delay = 0.537 ns ( 12.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.887 ns ( 87.86 % ) " "Info: Total interconnect delay = 3.887 ns ( 87.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.424 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.424 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 2.874ns 1.013ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.397 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.397 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[11] } { 0.000ns 2.874ns 0.986ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.424 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.424 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 2.874ns 1.013ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "../../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "cpu_0_jtag_debug_module.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0_jtag_debug_module.v" 222 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.925 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4756 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12]~4765 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4838 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4839 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4840 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.925 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[35]~4756 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[12]~4765 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4838 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4839 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr~4840 system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[11] } { 0.000ns 1.105ns 0.753ns 2.088ns 0.263ns 0.955ns 0.000ns } { 0.000ns 0.398ns 0.420ns 0.271ns 0.438ns 0.150ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.397 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.397 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|sr[11] } { 0.000ns 2.874ns 0.986ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.424 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.424 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 2.874ns 1.013ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 register system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|b_non_empty register system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|b_non_empty 391 ps " "Info: Minimum slack time is 391 ps for clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" between source register \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|b_non_empty\" and destination register \"system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|b_non_empty\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns + Shortest register register " "Info: + Shortest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|b_non_empty 1 REG LCFF_X29_Y13_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y13_N5; Fanout = 3; REG Node = 'system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|b_non_empty'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } "NODE_NAME" } } { "db/a_fefifo_7cf.tdf" "" { Text "C:/csce496/final_project/PROCESSOR/db/a_fefifo_7cf.tdf" 37 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|b_non_empty~143 2 COMB LCCOMB_X29_Y13_N4 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X29_Y13_N4; Fanout = 1; COMB Node = 'system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|b_non_empty~143'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.323 ns" { system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~143 } "NODE_NAME" } } { "db/a_fefifo_7cf.tdf" "" { Text "C:/csce496/final_project/PROCESSOR/db/a_fefifo_7cf.tdf" 37 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|b_non_empty 3 REG LCFF_X29_Y13_N5 3 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X29_Y13_N5; Fanout = 3; REG Node = 'system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|b_non_empty'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~143 system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } "NODE_NAME" } } { "db/a_fefifo_7cf.tdf" "" { Text "C:/csce496/final_project/PROCESSOR/db/a_fefifo_7cf.tdf" 37 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.407 ns" { system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~143 system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.407 ns" { system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~143 system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.016 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.016 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.358 ns " "Info: + Latch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 10.000 ns -2.358 ns  50 " "Info: Clock period of Destination clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" is 10.000 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.358 ns " "Info: - Launch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 10.000 ns -2.358 ns  50 " "Info: Clock period of Source clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" is 10.000 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 destination 2.655 ns + Longest register " "Info: + Longest clock path from clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" to destination register is 2.655 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G3 3158 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 3158; COMB Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.091 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.537 ns) 2.655 ns system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|b_non_empty 3 REG LCFF_X29_Y13_N5 3 " "Info: 3: + IC(1.027 ns) + CELL(0.537 ns) = 2.655 ns; Loc. = LCFF_X29_Y13_N5; Fanout = 3; REG Node = 'system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|b_non_empty'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.564 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } "NODE_NAME" } } { "db/a_fefifo_7cf.tdf" "" { Text "C:/csce496/final_project/PROCESSOR/db/a_fefifo_7cf.tdf" 37 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.23 % ) " "Info: Total cell delay = 0.537 ns ( 20.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.118 ns ( 79.77 % ) " "Info: Total interconnect delay = 2.118 ns ( 79.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } { 0.000ns 1.091ns 1.027ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 source 2.655 ns - Shortest register " "Info: - Shortest clock path from clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" to source register is 2.655 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G3 3158 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 3158; COMB Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.091 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.537 ns) 2.655 ns system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|b_non_empty 3 REG LCFF_X29_Y13_N5 3 " "Info: 3: + IC(1.027 ns) + CELL(0.537 ns) = 2.655 ns; Loc. = LCFF_X29_Y13_N5; Fanout = 3; REG Node = 'system_0:u0\|jtag_uart_0:the_jtag_uart_0\|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w\|scfifo:wfifo\|scfifo_1n21:auto_generated\|a_dpfifo_8t21:dpfifo\|a_fefifo_7cf:fifo_state\|b_non_empty'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.564 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } "NODE_NAME" } } { "db/a_fefifo_7cf.tdf" "" { Text "C:/csce496/final_project/PROCESSOR/db/a_fefifo_7cf.tdf" 37 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.23 % ) " "Info: Total cell delay = 0.537 ns ( 20.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.118 ns ( 79.77 % ) " "Info: Total interconnect delay = 2.118 ns ( 79.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } { 0.000ns 1.091ns 1.027ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } { 0.000ns 1.091ns 1.027ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } { 0.000ns 1.091ns 1.027ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "db/a_fefifo_7cf.tdf" "" { Text "C:/csce496/final_project/PROCESSOR/db/a_fefifo_7cf.tdf" 37 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "db/a_fefifo_7cf.tdf" "" { Text "C:/csce496/final_project/PROCESSOR/db/a_fefifo_7cf.tdf" 37 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } { 0.000ns 1.091ns 1.027ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } { 0.000ns 1.091ns 1.027ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.407 ns" { system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~143 system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.407 ns" { system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty~143 system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } { 0.000ns 1.091ns 1.027ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.655 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_1n21:auto_generated|a_dpfifo_8t21:dpfifo|a_fefifo_7cf:fifo_state|b_non_empty } { 0.000ns 1.091ns 1.027ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "CLOCK_50 register system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\] register system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\] 391 ps " "Info: Minimum slack time is 391 ps for clock \"CLOCK_50\" between source register \"system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\]\" and destination register \"system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns + Shortest register register " "Info: + Shortest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\] 1 REG LCFF_X3_Y7_N11 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X3_Y7_N11; Fanout = 2; REG Node = 'system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 341 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns system_0:u0\|sdram_0:the_sdram_0\|Selector0~8 2 COMB LCCOMB_X3_Y7_N10 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X3_Y7_N10; Fanout = 1; COMB Node = 'system_0:u0\|sdram_0:the_sdram_0\|Selector0~8'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.323 ns" { system_0:u0|sdram_0:the_sdram_0|i_cmd[3] system_0:u0|sdram_0:the_sdram_0|Selector0~8 } "NODE_NAME" } } { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 352 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\] 3 REG LCFF_X3_Y7_N11 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X3_Y7_N11; Fanout = 2; REG Node = 'system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { system_0:u0|sdram_0:the_sdram_0|Selector0~8 system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 341 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.407 ns" { system_0:u0|sdram_0:the_sdram_0|i_cmd[3] system_0:u0|sdram_0:the_sdram_0|Selector0~8 system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.407 ns" { system_0:u0|sdram_0:the_sdram_0|i_cmd[3] system_0:u0|sdram_0:the_sdram_0|Selector0~8 system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.016 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.016 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLOCK_50 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CLOCK_50\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLOCK_50 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLOCK_50\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.672 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 2.672 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 487 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 487; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.537 ns) 2.672 ns system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\] 3 REG LCFF_X3_Y7_N11 2 " "Info: 3: + IC(1.018 ns) + CELL(0.537 ns) = 2.672 ns; Loc. = LCFF_X3_Y7_N11; Fanout = 2; REG Node = 'system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.555 ns" { CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 341 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.49 % ) " "Info: Total cell delay = 1.536 ns ( 57.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.136 ns ( 42.51 % ) " "Info: Total interconnect delay = 1.136 ns ( 42.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.672 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.672 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.672 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to source register is 2.672 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 487 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 487; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.537 ns) 2.672 ns system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\] 3 REG LCFF_X3_Y7_N11 2 " "Info: 3: + IC(1.018 ns) + CELL(0.537 ns) = 2.672 ns; Loc. = LCFF_X3_Y7_N11; Fanout = 2; REG Node = 'system_0:u0\|sdram_0:the_sdram_0\|i_cmd\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.555 ns" { CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 341 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.49 % ) " "Info: Total cell delay = 1.536 ns ( 57.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.136 ns ( 42.51 % ) " "Info: Total interconnect delay = 1.136 ns ( 42.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.672 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.672 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.672 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.672 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.672 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.672 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 341 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 341 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.672 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.672 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.672 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.672 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.407 ns" { system_0:u0|sdram_0:the_sdram_0|i_cmd[3] system_0:u0|sdram_0:the_sdram_0|Selector0~8 system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.407 ns" { system_0:u0|sdram_0:the_sdram_0|i_cmd[3] system_0:u0|sdram_0:the_sdram_0|Selector0~8 system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.672 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.672 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.672 ns" { CLOCK_50 CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.672 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl system_0:u0|sdram_0:the_sdram_0|i_cmd[3] } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[21\] SRAM_DQ\[5\] CLOCK_50 8.985 ns register " "Info: tsu for register \"system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[21\]\" (data pin = \"SRAM_DQ\[5\]\", clock pin = \"CLOCK_50\") is 8.985 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.312 ns + Longest pin register " "Info: + Longest pin to register delay is 9.312 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SRAM_DQ\[5\] 1 PIN PIN_AB10 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB10; Fanout = 1; PIN Node = 'SRAM_DQ\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[5] } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.820 ns) 0.820 ns SRAM_DQ\[5\]~10 2 COMB IOC_X14_Y0_N1 4 " "Info: 2: + IC(0.000 ns) + CELL(0.820 ns) = 0.820 ns; Loc. = IOC_X14_Y0_N1; Fanout = 4; COMB Node = 'SRAM_DQ\[5\]~10'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.820 ns" { SRAM_DQ[5] SRAM_DQ[5]~10 } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.087 ns) + CELL(0.419 ns) 7.326 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[21\]~3166 3 COMB LCCOMB_X23_Y9_N6 1 " "Info: 3: + IC(6.087 ns) + CELL(0.419 ns) = 7.326 ns; Loc. = LCCOMB_X23_Y9_N6; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[21\]~3166'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.506 ns" { SRAM_DQ[5]~10 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3166 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 1644 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.801 ns) + CELL(0.437 ns) 8.564 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[21\]~3167 4 COMB LCCOMB_X23_Y13_N30 1 " "Info: 4: + IC(0.801 ns) + CELL(0.437 ns) = 8.564 ns; Loc. = LCCOMB_X23_Y13_N30; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[21\]~3167'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.238 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3166 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3167 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 1644 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.244 ns) + CELL(0.420 ns) 9.228 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[21\]~3168 5 COMB LCCOMB_X23_Y13_N22 1 " "Info: 5: + IC(0.244 ns) + CELL(0.420 ns) = 9.228 ns; Loc. = LCCOMB_X23_Y13_N22; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|cpu_0_data_master_readdata\[21\]~3168'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.664 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3167 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3168 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 1644 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 9.312 ns system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[21\] 6 REG LCFF_X23_Y13_N23 3 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 9.312 ns; Loc. = LCFF_X23_Y13_N23; Fanout = 3; REG Node = 'system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[21\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3168 system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[21] } "NODE_NAME" } } { "cpu_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0.v" 8538 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 23.41 % ) " "Info: Total cell delay = 2.180 ns ( 23.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.132 ns ( 76.59 % ) " "Info: Total interconnect delay = 7.132 ns ( 76.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.312 ns" { SRAM_DQ[5] SRAM_DQ[5]~10 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3166 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3167 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3168 system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.312 ns" { SRAM_DQ[5] SRAM_DQ[5]~10 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3166 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3167 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3168 system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[21] } { 0.000ns 0.000ns 6.087ns 0.801ns 0.244ns 0.000ns } { 0.000ns 0.820ns 0.419ns 0.437ns 0.420ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "cpu_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0.v" 8538 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_PLL_OFFSET" "CLOCK_50 SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 -2.358 ns - " "Info: - Offset between input clock \"CLOCK_50\" and output clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" is -2.358 ns" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 174 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 destination 2.649 ns - Shortest register " "Info: - Shortest clock path from clock \"SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1\" to destination register is 2.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl 2 COMB CLKCTRL_G3 3158 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 3158; COMB Node = 'SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.091 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.537 ns) 2.649 ns system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[21\] 3 REG LCFF_X23_Y13_N23 3 " "Info: 3: + IC(1.021 ns) + CELL(0.537 ns) = 2.649 ns; Loc. = LCFF_X23_Y13_N23; Fanout = 3; REG Node = 'system_0:u0\|cpu_0:the_cpu_0\|d_readdata_d1\[21\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.558 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[21] } "NODE_NAME" } } { "cpu_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0.v" 8538 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.27 % ) " "Info: Total cell delay = 0.537 ns ( 20.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.112 ns ( 79.73 % ) " "Info: Total interconnect delay = 2.112 ns ( 79.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.649 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.649 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[21] } { 0.000ns 1.091ns 1.021ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.312 ns" { SRAM_DQ[5] SRAM_DQ[5]~10 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3166 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3167 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3168 system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.312 ns" { SRAM_DQ[5] SRAM_DQ[5]~10 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3166 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3167 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_readdata[21]~3168 system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[21] } { 0.000ns 0.000ns 6.087ns 0.801ns 0.244ns 0.000ns } { 0.000ns 0.820ns 0.419ns 0.437ns 0.420ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.649 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.649 ns" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk1 SDRAM_PLL:PLL1|altpll:altpll_component|_clk1~clkctrl system_0:u0|cpu_0:the_cpu_0|d_readdata_d1[21] } { 0.000ns 1.091ns 1.021ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 I2C_SCLK I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[1\] 15.302 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"I2C_SCLK\" through register \"I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[1\]\" is 15.302 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 5.087 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 5.087 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 487 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 487; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.787 ns) 2.940 ns I2C_AV_Config:u1\|mI2C_CTRL_CLK 3 REG LCFF_X64_Y19_N15 3 " "Info: 3: + IC(1.036 ns) + CELL(0.787 ns) = 2.940 ns; Loc. = LCFF_X64_Y19_N15; Fanout = 3; REG Node = 'I2C_AV_Config:u1\|mI2C_CTRL_CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.823 ns" { CLOCK_50~clkctrl I2C_AV_Config:u1|mI2C_CTRL_CLK } "NODE_NAME" } } { "I2C_AV_Config.v" "" { Text "C:/csce496/final_project/PROCESSOR/I2C_AV_Config.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.589 ns) + CELL(0.000 ns) 3.529 ns I2C_AV_Config:u1\|mI2C_CTRL_CLK~clkctrl 4 COMB CLKCTRL_G7 46 " "Info: 4: + IC(0.589 ns) + CELL(0.000 ns) = 3.529 ns; Loc. = CLKCTRL_G7; Fanout = 46; COMB Node = 'I2C_AV_Config:u1\|mI2C_CTRL_CLK~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.589 ns" { I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl } "NODE_NAME" } } { "I2C_AV_Config.v" "" { Text "C:/csce496/final_project/PROCESSOR/I2C_AV_Config.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.537 ns) 5.087 ns I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[1\] 5 REG LCFF_X14_Y6_N11 17 " "Info: 5: + IC(1.021 ns) + CELL(0.537 ns) = 5.087 ns; Loc. = LCFF_X14_Y6_N11; Fanout = 17; REG Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.558 ns" { I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] } "NODE_NAME" } } { "I2C_Controller.v" "" { Text "C:/csce496/final_project/PROCESSOR/I2C_Controller.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 45.67 % ) " "Info: Total cell delay = 2.323 ns ( 45.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.764 ns ( 54.33 % ) " "Info: Total interconnect delay = 2.764 ns ( 54.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.087 ns" { CLOCK_50 CLOCK_50~clkctrl I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.087 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] } { 0.000ns 0.000ns 0.118ns 1.036ns 0.589ns 1.021ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "I2C_Controller.v" "" { Text "C:/csce496/final_project/PROCESSOR/I2C_Controller.v" 85 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.965 ns + Longest register pin " "Info: + Longest register to pin delay is 9.965 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[1\] 1 REG LCFF_X14_Y6_N11 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y6_N11; Fanout = 17; REG Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|SD_COUNTER\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] } "NODE_NAME" } } { "I2C_Controller.v" "" { Text "C:/csce496/final_project/PROCESSOR/I2C_Controller.v" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.412 ns) + CELL(0.438 ns) 1.850 ns I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~253 2 COMB LCCOMB_X14_Y5_N18 1 " "Info: 2: + IC(1.412 ns) + CELL(0.438 ns) = 1.850 ns; Loc. = LCCOMB_X14_Y5_N18; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~253'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.850 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~253 } "NODE_NAME" } } { "I2C_Controller.v" "" { Text "C:/csce496/final_project/PROCESSOR/I2C_Controller.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.458 ns) + CELL(0.438 ns) 2.746 ns I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~254 3 COMB LCCOMB_X14_Y5_N12 1 " "Info: 3: + IC(0.458 ns) + CELL(0.438 ns) = 2.746 ns; Loc. = LCCOMB_X14_Y5_N12; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~254'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.896 ns" { I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~253 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~254 } "NODE_NAME" } } { "I2C_Controller.v" "" { Text "C:/csce496/final_project/PROCESSOR/I2C_Controller.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.150 ns) 3.628 ns I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~255 4 COMB LCCOMB_X14_Y7_N28 1 " "Info: 4: + IC(0.732 ns) + CELL(0.150 ns) = 3.628 ns; Loc. = LCCOMB_X14_Y7_N28; Fanout = 1; COMB Node = 'I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~255'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.882 ns" { I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~254 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 } "NODE_NAME" } } { "I2C_Controller.v" "" { Text "C:/csce496/final_project/PROCESSOR/I2C_Controller.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.529 ns) + CELL(2.808 ns) 9.965 ns I2C_SCLK 5 PIN PIN_A6 0 " "Info: 5: + IC(3.529 ns) + CELL(2.808 ns) = 9.965 ns; Loc. = PIN_A6; Fanout = 0; PIN Node = 'I2C_SCLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.337 ns" { I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 I2C_SCLK } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 255 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.834 ns ( 38.47 % ) " "Info: Total cell delay = 3.834 ns ( 38.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.131 ns ( 61.53 % ) " "Info: Total interconnect delay = 6.131 ns ( 61.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.965 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~253 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~254 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 I2C_SCLK } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.965 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~253 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~254 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 I2C_SCLK } { 0.000ns 1.412ns 0.458ns 0.732ns 3.529ns } { 0.000ns 0.438ns 0.438ns 0.150ns 2.808ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.087 ns" { CLOCK_50 CLOCK_50~clkctrl I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.087 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2C_AV_Config:u1|mI2C_CTRL_CLK I2C_AV_Config:u1|mI2C_CTRL_CLK~clkctrl I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] } { 0.000ns 0.000ns 0.118ns 1.036ns 0.589ns 1.021ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.965 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~253 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~254 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 I2C_SCLK } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.965 ns" { I2C_AV_Config:u1|I2C_Controller:u0|SD_COUNTER[1] I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~253 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~254 I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 I2C_SCLK } { 0.000ns 1.412ns 0.458ns 0.732ns 3.529ns } { 0.000ns 0.438ns 0.438ns 0.150ns 2.808ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "AUD_DACLRCK AUD_ADCLRCK 8.809 ns Longest " "Info: Longest tpd from source pin \"AUD_DACLRCK\" to destination pin \"AUD_ADCLRCK\" is 8.809 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AUD_DACLRCK 1 PIN PIN_C6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_C6; Fanout = 1; PIN Node = 'AUD_DACLRCK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 285 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.860 ns) 0.860 ns AUD_DACLRCK~0 2 COMB IOC_X1_Y36_N2 1 " "Info: 2: + IC(0.000 ns) + CELL(0.860 ns) = 0.860 ns; Loc. = IOC_X1_Y36_N2; Fanout = 1; COMB Node = 'AUD_DACLRCK~0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.860 ns" { AUD_DACLRCK AUD_DACLRCK~0 } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 285 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.141 ns) + CELL(2.808 ns) 8.809 ns AUD_ADCLRCK 3 PIN PIN_C5 0 " "Info: 3: + IC(5.141 ns) + CELL(2.808 ns) = 8.809 ns; Loc. = PIN_C5; Fanout = 0; PIN Node = 'AUD_ADCLRCK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.949 ns" { AUD_DACLRCK~0 AUD_ADCLRCK } "NODE_NAME" } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 283 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.668 ns ( 41.64 % ) " "Info: Total cell delay = 3.668 ns ( 41.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.141 ns ( 58.36 % ) " "Info: Total interconnect delay = 5.141 ns ( 58.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.809 ns" { AUD_DACLRCK AUD_DACLRCK~0 AUD_ADCLRCK } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.809 ns" { AUD_DACLRCK AUD_DACLRCK~0 AUD_ADCLRCK } { 0.000ns 0.000ns 5.141ns } { 0.000ns 0.860ns 2.808ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[0\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 1.643 ns register " "Info: th for register \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[0\]\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 1.643 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.452 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.452 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.874 ns) + CELL(0.000 ns) 2.874 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 191 " "Info: 2: + IC(2.874 ns) + CELL(0.000 ns) = 2.874 ns; Loc. = CLKCTRL_G0; Fanout = 191; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.874 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.537 ns) 4.452 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[0\] 3 REG LCFF_X32_Y16_N3 4 " "Info: 3: + IC(1.041 ns) + CELL(0.537 ns) = 4.452 ns; Loc. = LCFF_X32_Y16_N3; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.578 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } "NODE_NAME" } } { "../../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 12.06 % ) " "Info: Total cell delay = 0.537 ns ( 12.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.915 ns ( 87.94 % ) " "Info: Total interconnect delay = 3.915 ns ( 87.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.452 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.452 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } { 0.000ns 2.874ns 1.041ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "../../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.075 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.075 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y19_N0 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 22; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.841 ns) + CELL(0.150 ns) 2.991 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt~0 2 COMB LCCOMB_X32_Y16_N2 1 " "Info: 2: + IC(2.841 ns) + CELL(0.150 ns) = 2.991 ns; Loc. = LCCOMB_X32_Y16_N2; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt~0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.991 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt~0 } "NODE_NAME" } } { "../../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.075 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[0\] 3 REG LCFF_X32_Y16_N3 4 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 3.075 ns; Loc. = LCFF_X32_Y16_N3; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|tms_cnt\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt~0 sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } "NODE_NAME" } } { "../../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.234 ns ( 7.61 % ) " "Info: Total cell delay = 0.234 ns ( 7.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.841 ns ( 92.39 % ) " "Info: Total interconnect delay = 2.841 ns ( 92.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.075 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt~0 sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.075 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt~0 sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } { 0.000ns 2.841ns 0.000ns } { 0.000ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.452 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.452 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } { 0.000ns 2.874ns 1.041ns } { 0.000ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.075 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt~0 sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.075 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt~0 sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|tms_cnt[0] } { 0.000ns 2.841ns 0.000ns } { 0.000ns 0.150ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITAN_REQUIREMENTS_MET" "" "Info: All timing requirements were met. See Report window for more details." {  } {  } 0 0 "All timing requirements were met. See Report window for more details." 0 0}
{ "Warning" "WTAN_INVALID_ASSIGNMENTS_FOUND" "" "Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details" {  } {  } 0 0 "Found invalid timing assignments -- see Ignored Timing Assignments report for details" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 8 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 08 00:55:42 2007 " "Info: Processing ended: Sun Apr 08 00:55:42 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
