--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone II" INDATA_ACLR_A="NONE" INDATA_ACLR_B="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=512 NUMWORDS_B=512 OPERATION_MODE="BIDIR_DUAL_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_ACLR_B="NONE" OUTDATA_REG_A="UNREGISTERED" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=32 WIDTH_B=32 WIDTH_BYTEENA_B=4 WIDTHAD_A=9 WIDTHAD_B=9 WRCONTROL_ACLR_A="NONE" WRCONTROL_ACLR_B="NONE" address_a address_b byteena_b clock0 clock1 clocken0 clocken1 data_a data_b q_a q_b wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 6.0 cbx_altsyncram 2006:03:30:14:59:04:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


--  Copyright (C) 1991-2006 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


PARAMETERS
(
	PORT_A_ADDRESS_WIDTH = 1,
	PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
	PORT_A_DATA_WIDTH = 1,
	PORT_B_ADDRESS_WIDTH = 1,
	PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
	PORT_B_DATA_WIDTH = 1
);
FUNCTION cycloneii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
WITH ( 	CONNECTIVITY_CHECKING,	DATA_INTERLEAVE_OFFSET_IN_BITS,	DATA_INTERLEAVE_WIDTH_IN_BITS,	DONT_POWER_OPTIMIZE,	INIT_FILE,	INIT_FILE_LAYOUT,	LOGICAL_RAM_NAME,	mem_init0,	mem_init1,	MIXED_PORT_FEED_THROUGH_MODE,	OPERATION_MODE,	PORT_A_ADDRESS_WIDTH,	PORT_A_BYTE_ENABLE_MASK_WIDTH,	PORT_A_BYTE_SIZE,	PORT_A_DATA_OUT_CLEAR,	PORT_A_DATA_OUT_CLOCK,	PORT_A_DATA_WIDTH,	PORT_A_DISABLE_CE_ON_INPUT_REGISTERS,	PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS,	PORT_A_FIRST_ADDRESS,	PORT_A_FIRST_BIT_NUMBER,	PORT_A_LAST_ADDRESS,	PORT_A_LOGICAL_RAM_DEPTH,	PORT_A_LOGICAL_RAM_WIDTH,	PORT_B_ADDRESS_CLOCK,	PORT_B_ADDRESS_WIDTH,	PORT_B_BYTE_ENABLE_CLOCK,	PORT_B_BYTE_ENABLE_MASK_WIDTH,	PORT_B_BYTE_SIZE,	PORT_B_DATA_IN_CLOCK,	PORT_B_DATA_OUT_CLEAR,	PORT_B_DATA_OUT_CLOCK,	PORT_B_DATA_WIDTH,	PORT_B_DISABLE_CE_ON_INPUT_REGISTERS,	PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS,	PORT_B_FIRST_ADDRESS,	PORT_B_FIRST_BIT_NUMBER,	PORT_B_LAST_ADDRESS,	PORT_B_LOGICAL_RAM_DEPTH,	PORT_B_LOGICAL_RAM_WIDTH,	PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK,	POWER_UP_UNINITIALIZED,	RAM_BLOCK_TYPE,	SAFE_WRITE) 
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);

--synthesis_resources = M4K 64 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_a422
( 
	address_a[8..0]	:	input;
	address_b[8..0]	:	input;
	byteena_b[3..0]	:	input;
	clock0	:	input;
	clock1	:	input;
	clocken0	:	input;
	clocken1	:	input;
	data_a[31..0]	:	input;
	data_b[31..0]	:	input;
	q_a[31..0]	:	output;
	q_b[31..0]	:	output;
	wren_b	:	input;
) 
VARIABLE 
	ram_block1a0 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a1 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 1,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a2 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 2,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a3 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 3,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a4 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 4,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a5 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 5,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a6 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 6,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a7 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 7,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a8 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 8,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a9 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 9,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a10 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 10,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a11 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 11,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a12 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 12,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a13 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 13,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a14 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 14,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a15 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 15,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a16 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 16,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a17 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 17,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a18 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 18,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a19 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 19,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a20 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 20,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a21 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 21,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a22 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 22,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a23 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 23,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 23,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a24 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 24,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a25 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 25,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a26 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 26,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a27 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 27,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a28 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 28,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a29 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 29,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a30 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 30,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a31 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "old",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 9,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 511,
			PORT_A_LOGICAL_RAM_DEPTH = 512,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 9,
			PORT_B_BYTE_ENABLE_CLOCK = "clock1",
			PORT_B_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_B_BYTE_SIZE = 1,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 31,
			PORT_B_LAST_ADDRESS = 511,
			PORT_B_LOGICAL_RAM_DEPTH = 512,
			PORT_B_LOGICAL_RAM_WIDTH = 32,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "auto"
		);
	address_a_wire[8..0]	: WIRE;
	address_b_wire[8..0]	: WIRE;
	wren_a	: NODE;

BEGIN 
	ram_block1a[31..0].clk0 = clock0;
	ram_block1a[31..0].clk1 = clock1;
	ram_block1a[31..0].ena0 = clocken0;
	ram_block1a[31..0].ena1 = clocken1;
	ram_block1a[31..0].portaaddr[] = ( address_a_wire[8..0]);
	ram_block1a[0].portadatain[] = ( data_a[0..0]);
	ram_block1a[1].portadatain[] = ( data_a[1..1]);
	ram_block1a[2].portadatain[] = ( data_a[2..2]);
	ram_block1a[3].portadatain[] = ( data_a[3..3]);
	ram_block1a[4].portadatain[] = ( data_a[4..4]);
	ram_block1a[5].portadatain[] = ( data_a[5..5]);
	ram_block1a[6].portadatain[] = ( data_a[6..6]);
	ram_block1a[7].portadatain[] = ( data_a[7..7]);
	ram_block1a[8].portadatain[] = ( data_a[8..8]);
	ram_block1a[9].portadatain[] = ( data_a[9..9]);
	ram_block1a[10].portadatain[] = ( data_a[10..10]);
	ram_block1a[11].portadatain[] = ( data_a[11..11]);
	ram_block1a[12].portadatain[] = ( data_a[12..12]);
	ram_block1a[13].portadatain[] = ( data_a[13..13]);
	ram_block1a[14].portadatain[] = ( data_a[14..14]);
	ram_block1a[15].portadatain[] = ( data_a[15..15]);
	ram_block1a[16].portadatain[] = ( data_a[16..16]);
	ram_block1a[17].portadatain[] = ( data_a[17..17]);
	ram_block1a[18].portadatain[] = ( data_a[18..18]);
	ram_block1a[19].portadatain[] = ( data_a[19..19]);
	ram_block1a[20].portadatain[] = ( data_a[20..20]);
	ram_block1a[21].portadatain[] = ( data_a[21..21]);
	ram_block1a[22].portadatain[] = ( data_a[22..22]);
	ram_block1a[23].portadatain[] = ( data_a[23..23]);
	ram_block1a[24].portadatain[] = ( data_a[24..24]);
	ram_block1a[25].portadatain[] = ( data_a[25..25]);
	ram_block1a[26].portadatain[] = ( data_a[26..26]);
	ram_block1a[27].portadatain[] = ( data_a[27..27]);
	ram_block1a[28].portadatain[] = ( data_a[28..28]);
	ram_block1a[29].portadatain[] = ( data_a[29..29]);
	ram_block1a[30].portadatain[] = ( data_a[30..30]);
	ram_block1a[31].portadatain[] = ( data_a[31..31]);
	ram_block1a[31..0].portawe = wren_a;
	ram_block1a[31..0].portbaddr[] = ( address_b_wire[8..0]);
	ram_block1a[7..0].portbbyteenamasks[] = ( byteena_b[0..0]);
	ram_block1a[15..8].portbbyteenamasks[] = ( byteena_b[1..1]);
	ram_block1a[23..16].portbbyteenamasks[] = ( byteena_b[2..2]);
	ram_block1a[31..24].portbbyteenamasks[] = ( byteena_b[3..3]);
	ram_block1a[0].portbdatain[] = ( data_b[0..0]);
	ram_block1a[1].portbdatain[] = ( data_b[1..1]);
	ram_block1a[2].portbdatain[] = ( data_b[2..2]);
	ram_block1a[3].portbdatain[] = ( data_b[3..3]);
	ram_block1a[4].portbdatain[] = ( data_b[4..4]);
	ram_block1a[5].portbdatain[] = ( data_b[5..5]);
	ram_block1a[6].portbdatain[] = ( data_b[6..6]);
	ram_block1a[7].portbdatain[] = ( data_b[7..7]);
	ram_block1a[8].portbdatain[] = ( data_b[8..8]);
	ram_block1a[9].portbdatain[] = ( data_b[9..9]);
	ram_block1a[10].portbdatain[] = ( data_b[10..10]);
	ram_block1a[11].portbdatain[] = ( data_b[11..11]);
	ram_block1a[12].portbdatain[] = ( data_b[12..12]);
	ram_block1a[13].portbdatain[] = ( data_b[13..13]);
	ram_block1a[14].portbdatain[] = ( data_b[14..14]);
	ram_block1a[15].portbdatain[] = ( data_b[15..15]);
	ram_block1a[16].portbdatain[] = ( data_b[16..16]);
	ram_block1a[17].portbdatain[] = ( data_b[17..17]);
	ram_block1a[18].portbdatain[] = ( data_b[18..18]);
	ram_block1a[19].portbdatain[] = ( data_b[19..19]);
	ram_block1a[20].portbdatain[] = ( data_b[20..20]);
	ram_block1a[21].portbdatain[] = ( data_b[21..21]);
	ram_block1a[22].portbdatain[] = ( data_b[22..22]);
	ram_block1a[23].portbdatain[] = ( data_b[23..23]);
	ram_block1a[24].portbdatain[] = ( data_b[24..24]);
	ram_block1a[25].portbdatain[] = ( data_b[25..25]);
	ram_block1a[26].portbdatain[] = ( data_b[26..26]);
	ram_block1a[27].portbdatain[] = ( data_b[27..27]);
	ram_block1a[28].portbdatain[] = ( data_b[28..28]);
	ram_block1a[29].portbdatain[] = ( data_b[29..29]);
	ram_block1a[30].portbdatain[] = ( data_b[30..30]);
	ram_block1a[31].portbdatain[] = ( data_b[31..31]);
	ram_block1a[31..0].portbrewe = wren_b;
	address_a_wire[] = address_a[];
	address_b_wire[] = address_b[];
	q_a[] = ( ram_block1a[31..0].portadataout[0..0]);
	q_b[] = ( ram_block1a[31..0].portbdataout[0..0]);
	wren_a = GND;
END;
--VALID FILE
