--dcfifo CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_NUMWORDS=256 LPM_SHOWAHEAD="OFF" LPM_WIDTH=16 LPM_WIDTHU=8 OVERFLOW_CHECKING="ON" RDSYNC_DELAYPIPE=4 UNDERFLOW_CHECKING="ON" USE_EAB="ON" WRSYNC_DELAYPIPE=4 aclr data q rdclk rdreq wrclk wrfull wrreq CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" lpm_hint="RAM_BLOCK_TYPE=M4K" RAM_BLOCK_TYPE="M4K" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
--VERSION_BEGIN 6.0 cbx_a_gray2bin 2006:02:28:17:43:38:SJ cbx_a_graycounter 2006:03:13:11:03:08:SJ cbx_altdpram 2006:01:09:10:52:42:SJ cbx_altsyncram 2006:03:30:14:59:04:SJ cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_dcfifo 2006:03:30:14:19:28:SJ cbx_fifo_common 2006:01:09:11:23:34:SJ cbx_flex10ke 2006:01:09:11:13:48:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_compare 2006:01:09:11:15:40:SJ cbx_lpm_counter 2006:03:23:14:19:24:SJ cbx_lpm_decode 2006:01:09:11:16:44:SJ cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:04:14:11:14:36:SJ cbx_scfifo 2006:01:09:11:24:10:SJ cbx_stratix 2006:02:07:15:17:04:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


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--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
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--  without limitation, that your use is for the sole purpose of 
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--  applicable agreement for further details.


FUNCTION a_graycounter_g86 (aclr, clock, cnt_en)
RETURNS ( q[8..0]);
FUNCTION a_graycounter_b17 (aclr, clock, cnt_en)
RETURNS ( q[8..0]);
FUNCTION a_graycounter_a17 (aclr, clock, cnt_en)
RETURNS ( q[8..0]);
FUNCTION altsyncram_1731 (aclr1, address_a[7..0], address_b[7..0], addressstall_b, clock0, clock1, clocken1, data_a[15..0], wren_a)
RETURNS ( q_b[15..0]);
FUNCTION alt_synch_pipe_nc8 (clock, clrn, d[8..0])
RETURNS ( q[8..0]);
FUNCTION alt_synch_pipe_hn7 (clock, clrn, d[0..0])
RETURNS ( q[0..0]);
FUNCTION alt_synch_pipe_oc8 (clock, clrn, d[8..0])
RETURNS ( q[8..0]);

--synthesis_resources = lut 42 M4K 1 reg 88 
OPTIONS ALTERA_INTERNAL_OPTION = "AUTO_SHIFT_REGISTER_RECOGNITION=OFF;REMOVE_DUPLICATE_REGISTERS=OFF;suppress_da_rule_internal=d101;{-to p0addr} POWER_UP_LEVEL=LOW;{-to rdaclr} suppress_da_rule_internal=c106;{-to rdaclr} POWER_UP_LEVEL=LOW;{ -from ""rdptr_g"" -to ""ws_dgrp|dffpipe11|dffe12a"" }CUT=ON;{ -from ""delayed_wrptr_g"" -to ""rs_dgwp|dffpipe6|dffe7a"" }CUT=ON;{ -from ""previous_rdempty"" -to ""wrempty_reg|dffpipe9|dffe10a"" }CUT=ON";

SUBDESIGN dcfifo_e6c1
( 
	aclr	:	input;
	data[15..0]	:	input;
	q[15..0]	:	output;
	rdclk	:	input;
	rdempty	:	output;
	rdreq	:	input;
	wrclk	:	input;
	wrempty	:	output;
	wrfull	:	output;
	wrreq	:	input;
) 
VARIABLE 
	rdptr_g1p : a_graycounter_g86;
	wrptr_g1p : a_graycounter_b17;
	wrptr_gp : a_graycounter_a17;
	fifo_ram : altsyncram_1731;
	delayed_wrptr_g[8..0] : dffe;
	p0addr : dffe
		WITH (
			POWER_UP_HIGH = "OFF"
		);
	previous_rdempty : dffe;
	rdaclr : dffe
		WITH (
			POWER_UP_HIGH = "OFF"
		);
	rdptr_g[8..0] : dffe;
	rs_dgwp : alt_synch_pipe_nc8;
	wrempty_reg : alt_synch_pipe_hn7;
	ws_dgrp : alt_synch_pipe_oc8;
	rdempty_eq_comp_aeb_int	:	WIRE;
	rdempty_eq_comp_aeb	:	WIRE;
	rdempty_eq_comp_dataa[8..0]	:	WIRE;
	rdempty_eq_comp_datab[8..0]	:	WIRE;
	wrfull_eq_comp_aeb_int	:	WIRE;
	wrfull_eq_comp_aeb	:	WIRE;
	wrfull_eq_comp_dataa[8..0]	:	WIRE;
	wrfull_eq_comp_datab[8..0]	:	WIRE;
	int_rdempty	: WIRE;
	int_wrempty	: WIRE;
	int_wrfull	: WIRE;
	ram_address_a[7..0]	: WIRE;
	ram_address_b[7..0]	: WIRE;
	rdcnt_addr_ena	: WIRE;
	valid_rdreq	: WIRE;
	valid_wrreq	: WIRE;
	wrptr_gs[8..0]	: WIRE;

BEGIN 
	rdptr_g1p.aclr = (! rdaclr.Q);
	rdptr_g1p.clock = rdclk;
	rdptr_g1p.cnt_en = rdcnt_addr_ena;
	wrptr_g1p.aclr = aclr;
	wrptr_g1p.clock = wrclk;
	wrptr_g1p.cnt_en = valid_wrreq;
	wrptr_gp.aclr = aclr;
	wrptr_gp.clock = wrclk;
	wrptr_gp.cnt_en = valid_wrreq;
	fifo_ram.aclr1 = aclr;
	fifo_ram.address_a[] = ram_address_a[];
	fifo_ram.address_b[] = ram_address_b[];
	fifo_ram.addressstall_b = (! rdcnt_addr_ena);
	fifo_ram.clock0 = wrclk;
	fifo_ram.clock1 = rdclk;
	fifo_ram.clocken1 = valid_rdreq;
	fifo_ram.data_a[] = data[];
	fifo_ram.wren_a = valid_wrreq;
	delayed_wrptr_g[].CLK = wrclk;
	delayed_wrptr_g[].CLRN = (! aclr);
	delayed_wrptr_g[].D = wrptr_gp.q[];
	p0addr.CLK = rdclk;
	p0addr.CLRN = rdaclr.Q;
	p0addr.D = B"1";
	previous_rdempty.CLK = rdclk;
	previous_rdempty.CLRN = (! aclr);
	previous_rdempty.D = (! int_rdempty);
	rdaclr.CLK = (! rdclk);
	rdaclr.CLRN = (! aclr);
	rdaclr.D = B"1";
	rdptr_g[].CLK = rdclk;
	rdptr_g[].CLRN = (! aclr);
	rdptr_g[].D = rdptr_g1p.q[];
	rdptr_g[].ENA = valid_rdreq;
	rs_dgwp.clock = rdclk;
	rs_dgwp.clrn = (! aclr);
	rs_dgwp.d[] = delayed_wrptr_g[].Q;
	wrempty_reg.clock = wrclk;
	wrempty_reg.clrn = (! aclr);
	wrempty_reg.d[] = previous_rdempty.Q;
	ws_dgrp.clock = wrclk;
	ws_dgrp.clrn = (! aclr);
	ws_dgrp.d[] = rdptr_g[].Q;
	IF (rdempty_eq_comp_dataa[] == rdempty_eq_comp_datab[]) THEN
		rdempty_eq_comp_aeb_int = VCC;
	ELSE
		rdempty_eq_comp_aeb_int = GND;
	END IF;
	rdempty_eq_comp_aeb = rdempty_eq_comp_aeb_int;
	rdempty_eq_comp_dataa[] = rs_dgwp.q[];
	rdempty_eq_comp_datab[] = rdptr_g[].Q;
	IF (wrfull_eq_comp_dataa[] == wrfull_eq_comp_datab[]) THEN
		wrfull_eq_comp_aeb_int = VCC;
	ELSE
		wrfull_eq_comp_aeb_int = GND;
	END IF;
	wrfull_eq_comp_aeb = wrfull_eq_comp_aeb_int;
	wrfull_eq_comp_dataa[] = ws_dgrp.q[];
	wrfull_eq_comp_datab[] = wrptr_gs[];
	int_rdempty = rdempty_eq_comp_aeb;
	int_wrempty = (! wrempty_reg.q[]);
	int_wrfull = wrfull_eq_comp_aeb;
	q[] = fifo_ram.q_b[];
	ram_address_a[] = ( (wrptr_gp.q[8..8] $ wrptr_gp.q[7..7]), wrptr_gp.q[6..0]);
	ram_address_b[] = ( (rdptr_g1p.q[8..8] $ rdptr_g1p.q[7..7]), rdptr_g1p.q[6..0]);
	rdcnt_addr_ena = (valid_rdreq # (! p0addr.Q));
	rdempty = int_rdempty;
	valid_rdreq = (rdreq & (! int_rdempty));
	valid_wrreq = (wrreq & (! int_wrfull));
	wrempty = int_wrempty;
	wrfull = int_wrfull;
	wrptr_gs[] = ( (! wrptr_gp.q[8..8]), (! wrptr_gp.q[7..7]), wrptr_gp.q[6..0]);
END;
--VALID FILE
