{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 08 00:52:34 2007 " "Info: Processing started: Sun Apr 08 00:52:34 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DE2_NIOS_DEVICE_LED -c DE2_NIOS_DEVICE_LED " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DE2_NIOS_DEVICE_LED -c DE2_NIOS_DEVICE_LED" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "DE2_NIOS_DEVICE_LED EP2C35F672C6 " "Info: Selected device EP2C35F672C6 for design \"DE2_NIOS_DEVICE_LED\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "SDRAM_PLL:PLL1\|altpll:altpll_component\|pll Cyclone II " "Info: Implemented PLL \"SDRAM_PLL:PLL1\|altpll:altpll_component\|pll\" as Cyclone II PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk0 1 1 -54 -3000 " "Info: Implementing clock multiplication of 1, clock division of 1, and phase shift of -54 degrees (-3000 ps) for SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk0 port" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0} { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 2 1 0 0 " "Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 port" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 764 3 0 } }  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0}  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "Implemented PLL \"%1!s!\" as %2!s! PLL type" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50 (placed in PIN N2 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CLOCK_50 (placed in PIN N2 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 174 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk0 (placed in counter C2 of PLL_1) " "Info: Automatically promoted node SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk0 (placed in counter C2 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations External Clock Output CLKCTRL_X0_Y1_N1 " "Info: Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_X0_Y1_N1" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk0" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 (placed in counter C0 of PLL_1) " "Info: Automatically promoted node SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk1 (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SDRAM_PLL:PLL1\|altpll:altpll_component\|_clk0" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SDRAM_PLL:PLL1|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Info: Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "I2C_AV_Config:u1\|mI2C_CTRL_CLK  " "Info: Automatically promoted node I2C_AV_Config:u1\|mI2C_CTRL_CLK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~255 " "Info: Destination node I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~255" {  } { { "I2C_Controller.v" "" { Text "C:/csce496/final_project/PROCESSOR/I2C_Controller.v" 62 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u1\|I2C_Controller:u0\|I2C_SCLK~255" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|I2C_Controller:u0|I2C_SCLK~255 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "I2C_AV_Config:u1\|mI2C_CTRL_CLK~79 " "Info: Destination node I2C_AV_Config:u1\|mI2C_CTRL_CLK~79" {  } { { "I2C_AV_Config.v" "" { Text "C:/csce496/final_project/PROCESSOR/I2C_AV_Config.v" 16 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u1\|mI2C_CTRL_CLK~79" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|mI2C_CTRL_CLK~79 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|mI2C_CTRL_CLK~79 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "I2C_AV_Config.v" "" { Text "C:/csce496/final_project/PROCESSOR/I2C_AV_Config.v" 16 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "I2C_AV_Config:u1\|mI2C_CTRL_CLK" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|mI2C_CTRL_CLK } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { I2C_AV_Config:u1|mI2C_CTRL_CLK } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~UPDATEUSER  " "Info: Automatically promoted node altera_internal_jtag~UPDATEUSER " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updateir~112 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updateir~112" {  } { { "cpu_0_jtag_debug_module.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0_jtag_debug_module.v" 141 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updateir~112" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir~112 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updateir~112 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updatedr~99 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updatedr~99" {  } { { "cpu_0_jtag_debug_module.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0_jtag_debug_module.v" 140 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|st_updatedr~99" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr~99 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|st_updatedr~99 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out  " "Info: Automatically promoted node system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|jtag_break~47 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|jtag_break~47" {  } { { "cpu_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0.v" 764 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|jtag_break~47" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|jtag_break~47 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|jtag_break~47 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch~183 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch~183" {  } { { "cpu_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0.v" 747 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch~183" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch~183 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch~183 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 5248 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_out } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_out } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch\|data_out  " "Info: Automatically promoted node system_0:u0\|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch\|data_out " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|sdram_0:the_sdram_0\|active_addr\[20\]~426 " "Info: Destination node system_0:u0\|sdram_0:the_sdram_0\|active_addr\[20\]~426" {  } { { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 421 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|sdram_0:the_sdram_0\|active_addr\[20\]~426" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|active_addr[20]~426 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|active_addr[20]~426 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|sdram_0:the_sdram_0\|active_cs_n~187 " "Info: Destination node system_0:u0\|sdram_0:the_sdram_0\|active_cs_n~187" {  } { { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 207 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|sdram_0:the_sdram_0\|active_cs_n~187" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|active_cs_n~187 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|active_cs_n~187 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|sdram_0:the_sdram_0\|active_cs_n~188 " "Info: Destination node system_0:u0\|sdram_0:the_sdram_0\|active_cs_n~188" {  } { { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 207 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|sdram_0:the_sdram_0\|active_cs_n~188" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|active_cs_n~188 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|active_cs_n~188 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|sdram_0:the_sdram_0\|i_refs\[0\] " "Info: Destination node system_0:u0\|sdram_0:the_sdram_0\|i_refs\[0\]" {  } { { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 341 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|sdram_0:the_sdram_0\|i_refs\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|i_refs[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|i_refs[0] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|sdram_0:the_sdram_0\|i_refs\[2\] " "Info: Destination node system_0:u0\|sdram_0:the_sdram_0\|i_refs\[2\]" {  } { { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 341 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|sdram_0:the_sdram_0\|i_refs\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|i_refs[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|i_refs[2] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|sdram_0:the_sdram_0\|i_refs\[1\] " "Info: Destination node system_0:u0\|sdram_0:the_sdram_0\|i_refs\[1\]" {  } { { "sdram_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/sdram_0.v" 341 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|sdram_0:the_sdram_0\|i_refs\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|i_refs[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|sdram_0:the_sdram_0|i_refs[1] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 5293 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch\|data_out" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch|data_out } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch|data_out } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|CLR_SIGNAL  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|CLR_SIGNAL " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|ir\[1\]~0 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|ir\[1\]~0" {  } { { "cpu_0_jtag_debug_module.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0_jtag_debug_module.v" 222 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper\|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1\|ir\[1\]~0" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|ir[1]~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_jtag_debug_module_wrapper:the_cpu_0_jtag_debug_module_wrapper|cpu_0_jtag_debug_module:the_cpu_0_jtag_debug_module1|ir[1]~0 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch~182 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch~182" {  } { { "cpu_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0.v" 747 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch~182" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch~182 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch~182 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch~183 " "Info: Destination node system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch~183" {  } { { "cpu_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0.v" 747 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|cpu_0:the_cpu_0\|cpu_0_nios2_oci:the_cpu_0_nios2_oci\|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug\|resetlatch~183" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch~183 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|cpu_0_nios2_oci:the_cpu_0_nios2_oci|cpu_0_nios2_oci_debug:the_cpu_0_nios2_oci_debug|resetlatch~183 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "../../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|CLR_SIGNAL" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]  " "Info: Automatically promoted node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~436 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~436" {  } { { "../../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1135 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~436" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~436 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~436 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5 " "Info: Destination node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5" {  } { { "../../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1135 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~5" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~5 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0}  } { { "../../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "system_0:u0\|reset_n_sources~1  " "Info: Automatically promoted node system_0:u0\|reset_n_sources~1 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 5584 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|reset_n_sources~1" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|reset_n_sources~1 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|reset_n_sources~1 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Info" "IFSAC_FSAC_IGNORED_FAST_REGISTER_IO_ASSIGNMENTS" "" "Info: Ignoring invalid fast I/O register assignments" {  } {  } 0 0 "Ignoring invalid fast I/O register assignments" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:07 " "Info: Finished register packing: elapsed time is 00:00:07" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "18 EC " "Extra Info: Packed 18 registers into blocks of type EC" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "117 I/O " "Extra Info: Packed 117 registers into blocks of type I/O" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "64 Embedded multiplier block " "Extra Info: Packed 64 registers into blocks of type Embedded multiplier block" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "73 " "Extra Info: Created 73 register duplicates" {  } {  } 1 0 "Created %1!d! register duplicates" 0 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Warning" "WCUT_PLL_NON_ZDB_COMP_CLK_FEEDING_IO" "SDRAM_PLL:PLL1\|altpll:altpll_component\|pll compensate_clock 0 " "Warning: PLL \"SDRAM_PLL:PLL1\|altpll:altpll_component\|pll\" is in normal or source synchronous mode with output clock \"compensate_clock\" set to clk\[0\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "SDRAM_PLL.v" "" { Text "C:/csce496/final_project/PROCESSOR/SDRAM_PLL.v" 83 -1 0 } } { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 328 -1 0 } }  } 0 0 "PLL \"%1!s!\" is in normal or source synchronous mode with output clock \"%2!s!\" set to clk\[%3!d!\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:18 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:18" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:54 " "Info: Fitter placement operations ending: elapsed time is 00:00:54" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.524 ns register register " "Info: Estimated most critical path is register to register delay of 8.524 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns system_0:u0\|cpu_0:the_cpu_0\|d_address\[23\] 1 REG LAB_X21_Y11 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X21_Y11; Fanout = 5; REG Node = 'system_0:u0\|cpu_0:the_cpu_0\|d_address\[23\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0:the_cpu_0|d_address[23] } "NODE_NAME" } } { "cpu_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/cpu_0.v" 8484 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.933 ns) + CELL(0.150 ns) 1.083 ns system_0:u0\|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0\|cpu_0_data_master_requests_sram_0_avalon_slave_0~291 2 COMB LAB_X24_Y11 2 " "Info: 2: + IC(0.933 ns) + CELL(0.150 ns) = 1.083 ns; Loc. = LAB_X24_Y11; Fanout = 2; COMB Node = 'system_0:u0\|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0\|cpu_0_data_master_requests_sram_0_avalon_slave_0~291'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.083 ns" { system_0:u0|cpu_0:the_cpu_0|d_address[23] system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|cpu_0_data_master_requests_sram_0_avalon_slave_0~291 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 3751 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.438 ns) 1.648 ns system_0:u0\|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0\|cpu_0_data_master_requests_sram_0_avalon_slave_0~292 3 COMB LAB_X24_Y11 5 " "Info: 3: + IC(0.127 ns) + CELL(0.438 ns) = 1.648 ns; Loc. = LAB_X24_Y11; Fanout = 5; COMB Node = 'system_0:u0\|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0\|cpu_0_data_master_requests_sram_0_avalon_slave_0~292'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|cpu_0_data_master_requests_sram_0_avalon_slave_0~291 system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|cpu_0_data_master_requests_sram_0_avalon_slave_0~292 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 3751 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.904 ns) + CELL(0.419 ns) 2.971 ns system_0:u0\|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0\|cpu_0_data_master_arbiterlock~19 4 COMB LAB_X20_Y13 2 " "Info: 4: + IC(0.904 ns) + CELL(0.419 ns) = 2.971 ns; Loc. = LAB_X20_Y13; Fanout = 2; COMB Node = 'system_0:u0\|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0\|cpu_0_data_master_arbiterlock~19'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.323 ns" { system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|cpu_0_data_master_requests_sram_0_avalon_slave_0~292 system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|cpu_0_data_master_arbiterlock~19 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 3781 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.150 ns) 3.536 ns system_0:u0\|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0\|cpu_0_instruction_master_qualified_request_sram_0_avalon_slave_0 5 COMB LAB_X20_Y13 10 " "Info: 5: + IC(0.415 ns) + CELL(0.150 ns) = 3.536 ns; Loc. = LAB_X20_Y13; Fanout = 10; COMB Node = 'system_0:u0\|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0\|cpu_0_instruction_master_qualified_request_sram_0_avalon_slave_0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|cpu_0_data_master_arbiterlock~19 system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|cpu_0_instruction_master_qualified_request_sram_0_avalon_slave_0 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 3753 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.275 ns) 4.101 ns system_0:u0\|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0\|sram_0_avalon_slave_0_grant_vector\[1\]~44 6 COMB LAB_X20_Y13 28 " "Info: 6: + IC(0.290 ns) + CELL(0.275 ns) = 4.101 ns; Loc. = LAB_X20_Y13; Fanout = 28; COMB Node = 'system_0:u0\|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0\|sram_0_avalon_slave_0_grant_vector\[1\]~44'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|cpu_0_instruction_master_qualified_request_sram_0_avalon_slave_0 system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|sram_0_avalon_slave_0_grant_vector[1]~44 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 3826 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.892 ns) + CELL(0.437 ns) 5.430 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_count_enable~591 7 COMB LAB_X24_Y9 1 " "Info: 7: + IC(0.892 ns) + CELL(0.437 ns) = 5.430 ns; Loc. = LAB_X24_Y9; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_count_enable~591'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.329 ns" { system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|sram_0_avalon_slave_0_grant_vector[1]~44 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~591 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 1730 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.438 ns) 5.995 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_count_enable~595 8 COMB LAB_X24_Y9 1 " "Info: 8: + IC(0.127 ns) + CELL(0.438 ns) = 5.995 ns; Loc. = LAB_X24_Y9; Fanout = 1; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_count_enable~595'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~591 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~595 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 1730 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.145 ns) + CELL(0.420 ns) 6.560 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_count_enable~596 9 COMB LAB_X24_Y9 6 " "Info: 9: + IC(0.145 ns) + CELL(0.420 ns) = 6.560 ns; Loc. = LAB_X24_Y9; Fanout = 6; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_count_enable~596'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~595 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~596 } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 1730 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.145 ns) + CELL(0.420 ns) 7.125 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|always7~18 10 COMB LAB_X24_Y9 8 " "Info: 10: + IC(0.145 ns) + CELL(0.420 ns) = 7.125 ns; Loc. = LAB_X24_Y9; Fanout = 8; COMB Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|always7~18'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~596 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~18 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.739 ns) + CELL(0.660 ns) 8.524 ns system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_8_reg_segment_2\[6\] 11 REG LAB_X23_Y13 1 " "Info: 11: + IC(0.739 ns) + CELL(0.660 ns) = 8.524 ns; Loc. = LAB_X23_Y13; Fanout = 1; REG Node = 'system_0:u0\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\|dbs_8_reg_segment_2\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.399 ns" { system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~18 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } "NODE_NAME" } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 1932 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.807 ns ( 44.66 % ) " "Info: Total cell delay = 3.807 ns ( 44.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.717 ns ( 55.34 % ) " "Info: Total interconnect delay = 4.717 ns ( 55.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.524 ns" { system_0:u0|cpu_0:the_cpu_0|d_address[23] system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|cpu_0_data_master_requests_sram_0_avalon_slave_0~291 system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|cpu_0_data_master_requests_sram_0_avalon_slave_0~292 system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|cpu_0_data_master_arbiterlock~19 system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|cpu_0_instruction_master_qualified_request_sram_0_avalon_slave_0 system_0:u0|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0|sram_0_avalon_slave_0_grant_vector[1]~44 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~591 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~595 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_count_enable~596 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|always7~18 system_0:u0|cpu_0_data_master_arbitrator:the_cpu_0_data_master|dbs_8_reg_segment_2[6] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 34 " "Info: Average interconnect usage is 5% of the available device resources. Peak interconnect usage is 34%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x22_y12 x32_y23 " "Info: The peak interconnect region extends from location x22_y12 to location x32_y23" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:14 " "Info: Fitter routing operations ending: elapsed time is 00:00:14" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "377 " "Warning: Found 377 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[0\] 0 " "Info: Pin \"HEX0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[1\] 0 " "Info: Pin \"HEX0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[2\] 0 " "Info: Pin \"HEX0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[3\] 0 " "Info: Pin \"HEX0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[4\] 0 " "Info: Pin \"HEX0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[5\] 0 " "Info: Pin \"HEX0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[6\] 0 " "Info: Pin \"HEX0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[0\] 0 " "Info: Pin \"HEX1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[1\] 0 " "Info: Pin \"HEX1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[2\] 0 " "Info: Pin \"HEX1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[3\] 0 " "Info: Pin \"HEX1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[4\] 0 " "Info: Pin \"HEX1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[5\] 0 " "Info: Pin \"HEX1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[6\] 0 " "Info: Pin \"HEX1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[0\] 0 " "Info: Pin \"HEX2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[1\] 0 " "Info: Pin \"HEX2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[2\] 0 " "Info: Pin \"HEX2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[3\] 0 " "Info: Pin \"HEX2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[4\] 0 " "Info: Pin \"HEX2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[5\] 0 " "Info: Pin \"HEX2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[6\] 0 " "Info: Pin \"HEX2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[0\] 0 " "Info: Pin \"HEX3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[1\] 0 " "Info: Pin \"HEX3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[2\] 0 " "Info: Pin \"HEX3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[3\] 0 " "Info: Pin \"HEX3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[4\] 0 " "Info: Pin \"HEX3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[5\] 0 " "Info: Pin \"HEX3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[6\] 0 " "Info: Pin \"HEX3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[0\] 0 " "Info: Pin \"HEX4\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[1\] 0 " "Info: Pin \"HEX4\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[2\] 0 " "Info: Pin \"HEX4\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[3\] 0 " "Info: Pin \"HEX4\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[4\] 0 " "Info: Pin \"HEX4\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[5\] 0 " "Info: Pin \"HEX4\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX4\[6\] 0 " "Info: Pin \"HEX4\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[0\] 0 " "Info: Pin \"HEX5\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[1\] 0 " "Info: Pin \"HEX5\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[2\] 0 " "Info: Pin \"HEX5\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[3\] 0 " "Info: Pin \"HEX5\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[4\] 0 " "Info: Pin \"HEX5\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[5\] 0 " "Info: Pin \"HEX5\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX5\[6\] 0 " "Info: Pin \"HEX5\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[0\] 0 " "Info: Pin \"HEX6\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[1\] 0 " "Info: Pin \"HEX6\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[2\] 0 " "Info: Pin \"HEX6\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[3\] 0 " "Info: Pin \"HEX6\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[4\] 0 " "Info: Pin \"HEX6\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[5\] 0 " "Info: Pin \"HEX6\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX6\[6\] 0 " "Info: Pin \"HEX6\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[0\] 0 " "Info: Pin \"HEX7\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[1\] 0 " "Info: Pin \"HEX7\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[2\] 0 " "Info: Pin \"HEX7\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[3\] 0 " "Info: Pin \"HEX7\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[4\] 0 " "Info: Pin \"HEX7\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[5\] 0 " "Info: Pin \"HEX7\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX7\[6\] 0 " "Info: Pin \"HEX7\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[0\] 0 " "Info: Pin \"LEDG\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[1\] 0 " "Info: Pin \"LEDG\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[2\] 0 " "Info: Pin \"LEDG\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[3\] 0 " "Info: Pin \"LEDG\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[4\] 0 " "Info: Pin \"LEDG\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[5\] 0 " "Info: Pin \"LEDG\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[6\] 0 " "Info: Pin \"LEDG\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[7\] 0 " "Info: Pin \"LEDG\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[8\] 0 " "Info: Pin \"LEDG\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[0\] 0 " "Info: Pin \"LEDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[1\] 0 " "Info: Pin \"LEDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[2\] 0 " "Info: Pin \"LEDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[3\] 0 " "Info: Pin \"LEDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[4\] 0 " "Info: Pin \"LEDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[5\] 0 " "Info: Pin \"LEDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[6\] 0 " "Info: Pin \"LEDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[7\] 0 " "Info: Pin \"LEDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[8\] 0 " "Info: Pin \"LEDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[9\] 0 " "Info: Pin \"LEDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[10\] 0 " "Info: Pin \"LEDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[11\] 0 " "Info: Pin \"LEDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[12\] 0 " "Info: Pin \"LEDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[13\] 0 " "Info: Pin \"LEDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[14\] 0 " "Info: Pin \"LEDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[15\] 0 " "Info: Pin \"LEDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[16\] 0 " "Info: Pin \"LEDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[17\] 0 " "Info: Pin \"LEDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "UART_TXD 0 " "Info: Pin \"UART_TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "IRDA_TXD 0 " "Info: Pin \"IRDA_TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[0\] 0 " "Info: Pin \"DRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[1\] 0 " "Info: Pin \"DRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[2\] 0 " "Info: Pin \"DRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[3\] 0 " "Info: Pin \"DRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[4\] 0 " "Info: Pin \"DRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[5\] 0 " "Info: Pin \"DRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[6\] 0 " "Info: Pin \"DRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[7\] 0 " "Info: Pin \"DRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[8\] 0 " "Info: Pin \"DRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[9\] 0 " "Info: Pin \"DRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[10\] 0 " "Info: Pin \"DRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[11\] 0 " "Info: Pin \"DRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_LDQM 0 " "Info: Pin \"DRAM_LDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_UDQM 0 " "Info: Pin \"DRAM_UDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_WE_N 0 " "Info: Pin \"DRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CAS_N 0 " "Info: Pin \"DRAM_CAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_RAS_N 0 " "Info: Pin \"DRAM_RAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CS_N 0 " "Info: Pin \"DRAM_CS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_0 0 " "Info: Pin \"DRAM_BA_0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_1 0 " "Info: Pin \"DRAM_BA_1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CLK 0 " "Info: Pin \"DRAM_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CKE 0 " "Info: Pin \"DRAM_CKE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[0\] 0 " "Info: Pin \"FL_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[1\] 0 " "Info: Pin \"FL_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[2\] 0 " "Info: Pin \"FL_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[3\] 0 " "Info: Pin \"FL_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[4\] 0 " "Info: Pin \"FL_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[5\] 0 " "Info: Pin \"FL_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[6\] 0 " "Info: Pin \"FL_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[7\] 0 " "Info: Pin \"FL_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[8\] 0 " "Info: Pin \"FL_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[9\] 0 " "Info: Pin \"FL_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[10\] 0 " "Info: Pin \"FL_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[11\] 0 " "Info: Pin \"FL_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[12\] 0 " "Info: Pin \"FL_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[13\] 0 " "Info: Pin \"FL_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[14\] 0 " "Info: Pin \"FL_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[15\] 0 " "Info: Pin \"FL_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[16\] 0 " "Info: Pin \"FL_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[17\] 0 " "Info: Pin \"FL_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[18\] 0 " "Info: Pin \"FL_ADDR\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[19\] 0 " "Info: Pin \"FL_ADDR\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[20\] 0 " "Info: Pin \"FL_ADDR\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[21\] 0 " "Info: Pin \"FL_ADDR\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_WE_N 0 " "Info: Pin \"FL_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_RST_N 0 " "Info: Pin \"FL_RST_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_OE_N 0 " "Info: Pin \"FL_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_CE_N 0 " "Info: Pin \"FL_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[0\] 0 " "Info: Pin \"SRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[1\] 0 " "Info: Pin \"SRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[2\] 0 " "Info: Pin \"SRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[3\] 0 " "Info: Pin \"SRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[4\] 0 " "Info: Pin \"SRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[5\] 0 " "Info: Pin \"SRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[6\] 0 " "Info: Pin \"SRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[7\] 0 " "Info: Pin \"SRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[8\] 0 " "Info: Pin \"SRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[9\] 0 " "Info: Pin \"SRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[10\] 0 " "Info: Pin \"SRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[11\] 0 " "Info: Pin \"SRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[12\] 0 " "Info: Pin \"SRAM_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[13\] 0 " "Info: Pin \"SRAM_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[14\] 0 " "Info: Pin \"SRAM_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[15\] 0 " "Info: Pin \"SRAM_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[16\] 0 " "Info: Pin \"SRAM_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[17\] 0 " "Info: Pin \"SRAM_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_UB_N 0 " "Info: Pin \"SRAM_UB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_LB_N 0 " "Info: Pin \"SRAM_LB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_WE_N 0 " "Info: Pin \"SRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_CE_N 0 " "Info: Pin \"SRAM_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_OE_N 0 " "Info: Pin \"SRAM_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_ADDR\[0\] 0 " "Info: Pin \"OTG_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_ADDR\[1\] 0 " "Info: Pin \"OTG_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_CS_N 0 " "Info: Pin \"OTG_CS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_RD_N 0 " "Info: Pin \"OTG_RD_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_WR_N 0 " "Info: Pin \"OTG_WR_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_RST_N 0 " "Info: Pin \"OTG_RST_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_FSPEED 0 " "Info: Pin \"OTG_FSPEED\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_LSPEED 0 " "Info: Pin \"OTG_LSPEED\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DACK0_N 0 " "Info: Pin \"OTG_DACK0_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DACK1_N 0 " "Info: Pin \"OTG_DACK1_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_ON 0 " "Info: Pin \"LCD_ON\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_BLON 0 " "Info: Pin \"LCD_BLON\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_RW 0 " "Info: Pin \"LCD_RW\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_EN 0 " "Info: Pin \"LCD_EN\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_RS 0 " "Info: Pin \"LCD_RS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CLK 0 " "Info: Pin \"SD_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TDO 0 " "Info: Pin \"TDO\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SCLK 0 " "Info: Pin \"I2C_SCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_CLK 0 " "Info: Pin \"VGA_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_HS 0 " "Info: Pin \"VGA_HS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_VS 0 " "Info: Pin \"VGA_VS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_BLANK 0 " "Info: Pin \"VGA_BLANK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_SYNC 0 " "Info: Pin \"VGA_SYNC\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[0\] 0 " "Info: Pin \"VGA_R\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[1\] 0 " "Info: Pin \"VGA_R\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[2\] 0 " "Info: Pin \"VGA_R\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[3\] 0 " "Info: Pin \"VGA_R\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[4\] 0 " "Info: Pin \"VGA_R\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[5\] 0 " "Info: Pin \"VGA_R\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[6\] 0 " "Info: Pin \"VGA_R\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[7\] 0 " "Info: Pin \"VGA_R\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[8\] 0 " "Info: Pin \"VGA_R\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[9\] 0 " "Info: Pin \"VGA_R\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[0\] 0 " "Info: Pin \"VGA_G\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[1\] 0 " "Info: Pin \"VGA_G\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[2\] 0 " "Info: Pin \"VGA_G\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[3\] 0 " "Info: Pin \"VGA_G\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[4\] 0 " "Info: Pin \"VGA_G\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[5\] 0 " "Info: Pin \"VGA_G\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[6\] 0 " "Info: Pin \"VGA_G\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[7\] 0 " "Info: Pin \"VGA_G\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[8\] 0 " "Info: Pin \"VGA_G\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[9\] 0 " "Info: Pin \"VGA_G\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[0\] 0 " "Info: Pin \"VGA_B\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[1\] 0 " "Info: Pin \"VGA_B\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[2\] 0 " "Info: Pin \"VGA_B\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[3\] 0 " "Info: Pin \"VGA_B\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[4\] 0 " "Info: Pin \"VGA_B\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[5\] 0 " "Info: Pin \"VGA_B\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[6\] 0 " "Info: Pin \"VGA_B\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[7\] 0 " "Info: Pin \"VGA_B\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[8\] 0 " "Info: Pin \"VGA_B\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[9\] 0 " "Info: Pin \"VGA_B\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_CMD 0 " "Info: Pin \"ENET_CMD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_CS_N 0 " "Info: Pin \"ENET_CS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_WR_N 0 " "Info: Pin \"ENET_WR_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_RD_N 0 " "Info: Pin \"ENET_RD_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_RST_N 0 " "Info: Pin \"ENET_RST_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_CLK 0 " "Info: Pin \"ENET_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACDAT 0 " "Info: Pin \"AUD_DACDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_XCK 0 " "Info: Pin \"AUD_XCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TD_RESET 0 " "Info: Pin \"TD_RESET\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[0\] 0 " "Info: Pin \"OTG_DATA\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[1\] 0 " "Info: Pin \"OTG_DATA\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[2\] 0 " "Info: Pin \"OTG_DATA\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[3\] 0 " "Info: Pin \"OTG_DATA\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[4\] 0 " "Info: Pin \"OTG_DATA\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[5\] 0 " "Info: Pin \"OTG_DATA\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[6\] 0 " "Info: Pin \"OTG_DATA\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[7\] 0 " "Info: Pin \"OTG_DATA\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[8\] 0 " "Info: Pin \"OTG_DATA\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[9\] 0 " "Info: Pin \"OTG_DATA\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[10\] 0 " "Info: Pin \"OTG_DATA\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[11\] 0 " "Info: Pin \"OTG_DATA\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[12\] 0 " "Info: Pin \"OTG_DATA\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[13\] 0 " "Info: Pin \"OTG_DATA\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[14\] 0 " "Info: Pin \"OTG_DATA\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "OTG_DATA\[15\] 0 " "Info: Pin \"OTG_DATA\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[0\] 0 " "Info: Pin \"LCD_DATA\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[1\] 0 " "Info: Pin \"LCD_DATA\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[2\] 0 " "Info: Pin \"LCD_DATA\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[3\] 0 " "Info: Pin \"LCD_DATA\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[4\] 0 " "Info: Pin \"LCD_DATA\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[5\] 0 " "Info: Pin \"LCD_DATA\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[6\] 0 " "Info: Pin \"LCD_DATA\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LCD_DATA\[7\] 0 " "Info: Pin \"LCD_DATA\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CMD 0 " "Info: Pin \"SD_CMD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[0\] 0 " "Info: Pin \"ENET_DATA\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[1\] 0 " "Info: Pin \"ENET_DATA\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[2\] 0 " "Info: Pin \"ENET_DATA\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[3\] 0 " "Info: Pin \"ENET_DATA\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[4\] 0 " "Info: Pin \"ENET_DATA\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[5\] 0 " "Info: Pin \"ENET_DATA\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[6\] 0 " "Info: Pin \"ENET_DATA\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[7\] 0 " "Info: Pin \"ENET_DATA\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[8\] 0 " "Info: Pin \"ENET_DATA\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[9\] 0 " "Info: Pin \"ENET_DATA\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[10\] 0 " "Info: Pin \"ENET_DATA\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[11\] 0 " "Info: Pin \"ENET_DATA\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[12\] 0 " "Info: Pin \"ENET_DATA\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[13\] 0 " "Info: Pin \"ENET_DATA\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[14\] 0 " "Info: Pin \"ENET_DATA\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "ENET_DATA\[15\] 0 " "Info: Pin \"ENET_DATA\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_BCLK 0 " "Info: Pin \"AUD_BCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[0\] 0 " "Info: Pin \"DRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[1\] 0 " "Info: Pin \"DRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[2\] 0 " "Info: Pin \"DRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[3\] 0 " "Info: Pin \"DRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[4\] 0 " "Info: Pin \"DRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[5\] 0 " "Info: Pin \"DRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[6\] 0 " "Info: Pin \"DRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[7\] 0 " "Info: Pin \"DRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[8\] 0 " "Info: Pin \"DRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[9\] 0 " "Info: Pin \"DRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[10\] 0 " "Info: Pin \"DRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[11\] 0 " "Info: Pin \"DRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[12\] 0 " "Info: Pin \"DRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[13\] 0 " "Info: Pin \"DRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[14\] 0 " "Info: Pin \"DRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[15\] 0 " "Info: Pin \"DRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[0\] 0 " "Info: Pin \"FL_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[1\] 0 " "Info: Pin \"FL_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[2\] 0 " "Info: Pin \"FL_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[3\] 0 " "Info: Pin \"FL_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[4\] 0 " "Info: Pin \"FL_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[5\] 0 " "Info: Pin \"FL_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[6\] 0 " "Info: Pin \"FL_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[7\] 0 " "Info: Pin \"FL_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[0\] 0 " "Info: Pin \"SRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[1\] 0 " "Info: Pin \"SRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[2\] 0 " "Info: Pin \"SRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[3\] 0 " "Info: Pin \"SRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[4\] 0 " "Info: Pin \"SRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[5\] 0 " "Info: Pin \"SRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[6\] 0 " "Info: Pin \"SRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[7\] 0 " "Info: Pin \"SRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[8\] 0 " "Info: Pin \"SRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[9\] 0 " "Info: Pin \"SRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[10\] 0 " "Info: Pin \"SRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[11\] 0 " "Info: Pin \"SRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[12\] 0 " "Info: Pin \"SRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[13\] 0 " "Info: Pin \"SRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[14\] 0 " "Info: Pin \"SRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[15\] 0 " "Info: Pin \"SRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT 0 " "Info: Pin \"SD_DAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT3 0 " "Info: Pin \"SD_DAT3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SDAT 0 " "Info: Pin \"I2C_SDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_ADCLRCK 0 " "Info: Pin \"AUD_ADCLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACLRCK 0 " "Info: Pin \"AUD_DACLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[0\] 0 " "Info: Pin \"GPIO_0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[1\] 0 " "Info: Pin \"GPIO_0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[2\] 0 " "Info: Pin \"GPIO_0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[3\] 0 " "Info: Pin \"GPIO_0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[4\] 0 " "Info: Pin \"GPIO_0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[5\] 0 " "Info: Pin \"GPIO_0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[6\] 0 " "Info: Pin \"GPIO_0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[7\] 0 " "Info: Pin \"GPIO_0\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[8\] 0 " "Info: Pin \"GPIO_0\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[9\] 0 " "Info: Pin \"GPIO_0\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[10\] 0 " "Info: Pin \"GPIO_0\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[11\] 0 " "Info: Pin \"GPIO_0\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[12\] 0 " "Info: Pin \"GPIO_0\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[13\] 0 " "Info: Pin \"GPIO_0\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[14\] 0 " "Info: Pin \"GPIO_0\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[15\] 0 " "Info: Pin \"GPIO_0\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[16\] 0 " "Info: Pin \"GPIO_0\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[17\] 0 " "Info: Pin \"GPIO_0\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[18\] 0 " "Info: Pin \"GPIO_0\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[19\] 0 " "Info: Pin \"GPIO_0\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[20\] 0 " "Info: Pin \"GPIO_0\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[21\] 0 " "Info: Pin \"GPIO_0\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[22\] 0 " "Info: Pin \"GPIO_0\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[23\] 0 " "Info: Pin \"GPIO_0\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[24\] 0 " "Info: Pin \"GPIO_0\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[25\] 0 " "Info: Pin \"GPIO_0\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[26\] 0 " "Info: Pin \"GPIO_0\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[27\] 0 " "Info: Pin \"GPIO_0\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[28\] 0 " "Info: Pin \"GPIO_0\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[29\] 0 " "Info: Pin \"GPIO_0\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[30\] 0 " "Info: Pin \"GPIO_0\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[31\] 0 " "Info: Pin \"GPIO_0\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[32\] 0 " "Info: Pin \"GPIO_0\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[33\] 0 " "Info: Pin \"GPIO_0\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[34\] 0 " "Info: Pin \"GPIO_0\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[35\] 0 " "Info: Pin \"GPIO_0\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[0\] 0 " "Info: Pin \"GPIO_1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[1\] 0 " "Info: Pin \"GPIO_1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[2\] 0 " "Info: Pin \"GPIO_1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[3\] 0 " "Info: Pin \"GPIO_1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[4\] 0 " "Info: Pin \"GPIO_1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[5\] 0 " "Info: Pin \"GPIO_1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[6\] 0 " "Info: Pin \"GPIO_1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[7\] 0 " "Info: Pin \"GPIO_1\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[8\] 0 " "Info: Pin \"GPIO_1\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[9\] 0 " "Info: Pin \"GPIO_1\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[10\] 0 " "Info: Pin \"GPIO_1\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[11\] 0 " "Info: Pin \"GPIO_1\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[12\] 0 " "Info: Pin \"GPIO_1\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[13\] 0 " "Info: Pin \"GPIO_1\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[14\] 0 " "Info: Pin \"GPIO_1\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[15\] 0 " "Info: Pin \"GPIO_1\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[16\] 0 " "Info: Pin \"GPIO_1\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[17\] 0 " "Info: Pin \"GPIO_1\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[18\] 0 " "Info: Pin \"GPIO_1\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[19\] 0 " "Info: Pin \"GPIO_1\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[20\] 0 " "Info: Pin \"GPIO_1\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[21\] 0 " "Info: Pin \"GPIO_1\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[22\] 0 " "Info: Pin \"GPIO_1\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[23\] 0 " "Info: Pin \"GPIO_1\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[24\] 0 " "Info: Pin \"GPIO_1\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[25\] 0 " "Info: Pin \"GPIO_1\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[26\] 0 " "Info: Pin \"GPIO_1\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[27\] 0 " "Info: Pin \"GPIO_1\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[28\] 0 " "Info: Pin \"GPIO_1\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[29\] 0 " "Info: Pin \"GPIO_1\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[30\] 0 " "Info: Pin \"GPIO_1\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[31\] 0 " "Info: Pin \"GPIO_1\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[32\] 0 " "Info: Pin \"GPIO_1\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[33\] 0 " "Info: Pin \"GPIO_1\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[34\] 0 " "Info: Pin \"GPIO_1\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[35\] 0 " "Info: Pin \"GPIO_1\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "system_0:u0\|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch\|data_out~clkctrl " "Info: Node system_0:u0\|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch\|data_out~clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_0:the_clock_0\|slave_readdata_p1\[0\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_0:the_clock_0\|slave_readdata_p1\[0\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_readdata_p1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_0:the_clock_0\|slave_readdata_p1\[0\]" } } } } { "clock_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_0.v" 790 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_readdata_p1[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_0:the_clock_0\|slave_readdata_p1\[7\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_0:the_clock_0\|slave_readdata_p1\[7\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_readdata_p1[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_0:the_clock_0\|slave_readdata_p1\[7\]" } } } } { "clock_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_0.v" 790 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_readdata_p1[7] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch|data_out~clkctrl } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch\|data_out~clkctrl" } } } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 5293 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_clk_50_domain_synch_module:system_0_reset_clk_50_domain_synch|data_out~clkctrl } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|CLR_SIGNAL~clkctrl " "Info: Node sld_hub:sld_hub_inst\|CLR_SIGNAL~clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[10\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[10\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[10\]" } } } } { "../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "C:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 250 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[10] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[8\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[8\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[8\]" } } } } { "../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "C:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 250 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[8] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[7\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[7\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[7\]" } } } } { "../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "C:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 250 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[7] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[9\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[9\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[9\]" } } } } { "../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "C:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 250 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[9] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[4\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[4\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[4\]" } } } } { "../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "C:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 250 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[4] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[3\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[3\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|td_shift\[3\]" } } } } { "../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "C:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 250 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|td_shift[3] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~clkctrl } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|CLR_SIGNAL~clkctrl" } } } } { "../../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|CLR_SIGNAL~clkctrl } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out~clkctrl " "Info: Node system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out~clkctrl uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[12\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[12\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_writedata_d1[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[12\]" } } } } { "clock_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_0.v" 808 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_writedata_d1[12] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[6\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[6\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_writedata_d1[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[6\]" } } } } { "clock_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_0.v" 808 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_writedata_d1[6] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[5\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[5\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_writedata_d1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[5\]" } } } } { "clock_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_0.v" 808 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_writedata_d1[5] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[4\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[4\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_writedata_d1[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[4\]" } } } } { "clock_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_0.v" 808 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_writedata_d1[4] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[7\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[7\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_writedata_d1[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[7\]" } } } } { "clock_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_0.v" 808 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_writedata_d1[7] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[10\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[10\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_writedata_d1[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[10\]" } } } } { "clock_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_0.v" 808 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_writedata_d1[10] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_0:the_clock_0\|slave_byteenable_d1\[0\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_0:the_clock_0\|slave_byteenable_d1\[0\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_byteenable_d1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_0:the_clock_0\|slave_byteenable_d1\[0\]" } } } } { "clock_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_0.v" 862 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_byteenable_d1[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[15\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[15\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_writedata_d1[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_0:the_clock_0\|slave_writedata_d1\[15\]" } } } } { "clock_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_0.v" 808 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_writedata_d1[15] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_1:the_clock_1\|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync\|data_in_d1 " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_1:the_clock_1\|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync\|data_in_d1 -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|data_in_d1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_1:the_clock_1\|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync\|data_in_d1" } } } } { "clock_1.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_1.v" 82 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|clock_1_master_write_done_sync_module:clock_1_master_write_done_sync|data_in_d1 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_0:the_clock_0\|slave_address_d1\[13\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_0:the_clock_0\|slave_address_d1\[13\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_address_d1[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_0:the_clock_0\|slave_address_d1\[13\]" } } } } { "clock_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_0.v" 826 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_address_d1[13] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[11\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[11\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[11\]" } } } } { "clock_1.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_1.v" 826 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[11] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[6\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[6\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[6\]" } } } } { "clock_1.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_1.v" 826 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[6] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[13\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[13\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[13\]" } } } } { "clock_1.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_1.v" 826 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[13] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[12\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[12\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[12\]" } } } } { "clock_1.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_1.v" 826 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[12] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_0:the_clock_0\|slave_address_d1\[17\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_0:the_clock_0\|slave_address_d1\[17\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_address_d1[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_0:the_clock_0\|slave_address_d1\[17\]" } } } } { "clock_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_0.v" 826 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_address_d1[17] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[9\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[9\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[9\]" } } } } { "clock_1.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_1.v" 826 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[9] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[17\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[17\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[17\]" } } } } { "clock_1.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_1.v" 826 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[17] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_0:the_clock_0\|slave_address_d1\[18\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_0:the_clock_0\|slave_address_d1\[18\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_address_d1[18] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_0:the_clock_0\|slave_address_d1\[18\]" } } } } { "clock_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_0.v" 826 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_address_d1[18] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[18\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[18\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[18] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[18\]" } } } } { "clock_1.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_1.v" 826 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[18] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[15\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[15\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[15\]" } } } } { "clock_1.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_1.v" 826 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[15] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_arb_addend\[0\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_arb_addend\[0\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_arb_addend\[0\]" } } } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 1449 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[19\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[19\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[19] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[19\]" } } } } { "clock_1.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_1.v" 826 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[19] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|d1_reasons_to_wait " "Info: Port clear -- assigned as a global for destination node system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|d1_reasons_to_wait -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|d1_reasons_to_wait } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|d1_reasons_to_wait" } } } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 1281 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|d1_reasons_to_wait } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_arb_addend\[1\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_arb_addend\[1\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module\|cpu_0_jtag_debug_module_arb_addend\[1\]" } } } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 1449 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|cpu_0_jtag_debug_module_arbitrator:the_cpu_0_jtag_debug_module|cpu_0_jtag_debug_module_arb_addend[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_0:the_clock_0\|slave_address_d1\[1\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_0:the_clock_0\|slave_address_d1\[1\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_address_d1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_0:the_clock_0\|slave_address_d1\[1\]" } } } } { "clock_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_0.v" 826 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_0:the_clock_0|slave_address_d1[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_1:the_clock_1\|slave_writedata_d1\[13\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_1:the_clock_1\|slave_writedata_d1\[13\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_writedata_d1[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_1:the_clock_1\|slave_writedata_d1\[13\]" } } } } { "clock_1.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_1.v" 808 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_writedata_d1[13] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[1\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[1\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_1:the_clock_1\|slave_address_d1\[1\]" } } } } { "clock_1.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_1.v" 826 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_address_d1[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|clock_1:the_clock_1\|slave_writedata_d1\[5\] " "Info: Port clear -- assigned as a global for destination node system_0:u0\|clock_1:the_clock_1\|slave_writedata_d1\[5\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_writedata_d1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|clock_1:the_clock_1\|slave_writedata_d1\[5\]" } } } } { "clock_1.v" "" { Text "C:/csce496/final_project/PROCESSOR/clock_1.v" 808 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|clock_1:the_clock_1|slave_writedata_d1[5] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|fifo_AF " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|fifo_AF -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|fifo_AF } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|fifo_AF" } } } } { "jtag_uart_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/jtag_uart_0.v" 559 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|fifo_AF } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|r_ena1 " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|r_ena1 -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|r_ena1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|r_ena1" } } } } { "../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "C:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 214 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|r_ena1 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|rvalid0 " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|rvalid0 -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rvalid0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|rvalid0" } } } } { "../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "C:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 206 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rvalid0 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate2 " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate2 -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate2" } } } } { "../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "C:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 213 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate2 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|t_dav " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|t_dav -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|t_dav } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|t_dav" } } } } { "jtag_uart_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/jtag_uart_0.v" 586 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|t_dav } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write1 " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write1 -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write1" } } } } { "../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "C:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 209 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write1 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|rvalid " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|rvalid -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rvalid } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|rvalid" } } } } { "../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "C:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 205 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|rvalid } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|t_pause~reg0 " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|t_pause~reg0 -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_pause~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|t_pause~reg0" } } } } { "../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "C:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 420 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_pause~reg0 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|t_ena~reg0 " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|t_ena~reg0 -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_ena~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|t_ena~reg0" } } } } { "../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "C:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 420 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|t_ena~reg0 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|r_val " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|r_val -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|r_val } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|r_val" } } } } { "jtag_uart_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/jtag_uart_0.v" 574 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|r_val } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write2 " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write2 -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|read_write2" } } } } { "../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "C:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 210 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|read_write2 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate1 " "Info: Port clear -- assigned as a global for destination node system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate1 -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|jtag_uart_0:the_jtag_uart_0\|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic\|jupdate1" } } } } { "../../../altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" "" { Text "C:/altera/quartus60/libraries/megafunctions/alt_jtag_atlantic.v" 212 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate1 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_out~clkctrl } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "system_0:u0\|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch\|data_out~clkctrl" } } } } { "system_0.v" "" { Text "C:/csce496/final_project/PROCESSOR/system_0.v" 5248 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { system_0:u0|system_0_reset_clk_domain_synch_module:system_0_reset_clk_domain_synch|data_out~clkctrl } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "118 " "Warning: Following 118 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[0\] a permanently disabled " "Info: Pin OTG_DATA\[0\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[1\] a permanently disabled " "Info: Pin OTG_DATA\[1\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[2\] a permanently disabled " "Info: Pin OTG_DATA\[2\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[3\] a permanently disabled " "Info: Pin OTG_DATA\[3\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[4\] a permanently disabled " "Info: Pin OTG_DATA\[4\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[5\] a permanently disabled " "Info: Pin OTG_DATA\[5\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[6\] a permanently disabled " "Info: Pin OTG_DATA\[6\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[7\] a permanently disabled " "Info: Pin OTG_DATA\[7\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[8\] a permanently disabled " "Info: Pin OTG_DATA\[8\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[9\] a permanently disabled " "Info: Pin OTG_DATA\[9\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[10\] a permanently disabled " "Info: Pin OTG_DATA\[10\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[11\] a permanently disabled " "Info: Pin OTG_DATA\[11\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[12\] a permanently disabled " "Info: Pin OTG_DATA\[12\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[13\] a permanently disabled " "Info: Pin OTG_DATA\[13\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[14\] a permanently disabled " "Info: Pin OTG_DATA\[14\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "OTG_DATA\[15\] a permanently disabled " "Info: Pin OTG_DATA\[15\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[0\] a permanently disabled " "Info: Pin LCD_DATA\[0\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[1\] a permanently disabled " "Info: Pin LCD_DATA\[1\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[2\] a permanently disabled " "Info: Pin LCD_DATA\[2\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[3\] a permanently disabled " "Info: Pin LCD_DATA\[3\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[4\] a permanently disabled " "Info: Pin LCD_DATA\[4\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[5\] a permanently disabled " "Info: Pin LCD_DATA\[5\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[6\] a permanently disabled " "Info: Pin LCD_DATA\[6\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "LCD_DATA\[7\] a permanently disabled " "Info: Pin LCD_DATA\[7\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SD_CMD a permanently disabled " "Info: Pin SD_CMD has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 251 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[0\] a permanently disabled " "Info: Pin ENET_DATA\[0\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[1\] a permanently disabled " "Info: Pin ENET_DATA\[1\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[2\] a permanently disabled " "Info: Pin ENET_DATA\[2\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[3\] a permanently disabled " "Info: Pin ENET_DATA\[3\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[4\] a permanently disabled " "Info: Pin ENET_DATA\[4\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[5\] a permanently disabled " "Info: Pin ENET_DATA\[5\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[6\] a permanently disabled " "Info: Pin ENET_DATA\[6\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[7\] a permanently disabled " "Info: Pin ENET_DATA\[7\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[8\] a permanently disabled " "Info: Pin ENET_DATA\[8\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[8\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[9\] a permanently disabled " "Info: Pin ENET_DATA\[9\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[9\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[10\] a permanently disabled " "Info: Pin ENET_DATA\[10\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[10\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[11\] a permanently disabled " "Info: Pin ENET_DATA\[11\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[11\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[12\] a permanently disabled " "Info: Pin ENET_DATA\[12\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[12\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[13\] a permanently disabled " "Info: Pin ENET_DATA\[13\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[13\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[14\] a permanently disabled " "Info: Pin ENET_DATA\[14\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[14\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "ENET_DATA\[15\] a permanently disabled " "Info: Pin ENET_DATA\[15\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[15\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_BCLK a permanently disabled " "Info: Pin AUD_BCLK has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 287 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SD_DAT a permanently disabled " "Info: Pin SD_DAT has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 249 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SD_DAT" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SD_DAT3 a permanently enabled " "Info: Pin SD_DAT3 has a permanently enabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 250 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SD_DAT3" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_ADCLRCK a permanently enabled " "Info: Pin AUD_ADCLRCK has a permanently enabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 283 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_DACLRCK a permanently disabled " "Info: Pin AUD_DACLRCK has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 285 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[0\] a permanently disabled " "Info: Pin GPIO_0\[0\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[1\] a permanently disabled " "Info: Pin GPIO_0\[1\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[2\] a permanently disabled " "Info: Pin GPIO_0\[2\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[3\] a permanently disabled " "Info: Pin GPIO_0\[3\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[4\] a permanently disabled " "Info: Pin GPIO_0\[4\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[5\] a permanently disabled " "Info: Pin GPIO_0\[5\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[6\] a permanently disabled " "Info: Pin GPIO_0\[6\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[7\] a permanently disabled " "Info: Pin GPIO_0\[7\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[8\] a permanently disabled " "Info: Pin GPIO_0\[8\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[9\] a permanently disabled " "Info: Pin GPIO_0\[9\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[10\] a permanently disabled " "Info: Pin GPIO_0\[10\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[11\] a permanently disabled " "Info: Pin GPIO_0\[11\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[12\] a permanently disabled " "Info: Pin GPIO_0\[12\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[13\] a permanently disabled " "Info: Pin GPIO_0\[13\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[14\] a permanently disabled " "Info: Pin GPIO_0\[14\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[15\] a permanently disabled " "Info: Pin GPIO_0\[15\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[16\] a permanently disabled " "Info: Pin GPIO_0\[16\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[17\] a permanently disabled " "Info: Pin GPIO_0\[17\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[18\] a permanently disabled " "Info: Pin GPIO_0\[18\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[19\] a permanently disabled " "Info: Pin GPIO_0\[19\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[20\] a permanently disabled " "Info: Pin GPIO_0\[20\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[21\] a permanently disabled " "Info: Pin GPIO_0\[21\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[22\] a permanently disabled " "Info: Pin GPIO_0\[22\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[23\] a permanently disabled " "Info: Pin GPIO_0\[23\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[24\] a permanently disabled " "Info: Pin GPIO_0\[24\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[25\] a permanently disabled " "Info: Pin GPIO_0\[25\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[26\] a permanently disabled " "Info: Pin GPIO_0\[26\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[27\] a permanently disabled " "Info: Pin GPIO_0\[27\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[28\] a permanently disabled " "Info: Pin GPIO_0\[28\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[29\] a permanently disabled " "Info: Pin GPIO_0\[29\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[30\] a permanently disabled " "Info: Pin GPIO_0\[30\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[31\] a permanently disabled " "Info: Pin GPIO_0\[31\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[32\] a permanently disabled " "Info: Pin GPIO_0\[32\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[33\] a permanently disabled " "Info: Pin GPIO_0\[33\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[34\] a permanently disabled " "Info: Pin GPIO_0\[34\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[35\] a permanently disabled " "Info: Pin GPIO_0\[35\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Info: Pin GPIO_1\[0\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Info: Pin GPIO_1\[1\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Info: Pin GPIO_1\[2\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Info: Pin GPIO_1\[3\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Info: Pin GPIO_1\[4\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Info: Pin GPIO_1\[5\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Info: Pin GPIO_1\[6\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Info: Pin GPIO_1\[7\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Info: Pin GPIO_1\[8\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Info: Pin GPIO_1\[9\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Info: Pin GPIO_1\[10\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Info: Pin GPIO_1\[11\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Info: Pin GPIO_1\[12\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Info: Pin GPIO_1\[13\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Info: Pin GPIO_1\[14\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Info: Pin GPIO_1\[15\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Info: Pin GPIO_1\[16\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Info: Pin GPIO_1\[17\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Info: Pin GPIO_1\[18\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Info: Pin GPIO_1\[19\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Info: Pin GPIO_1\[20\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Info: Pin GPIO_1\[21\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Info: Pin GPIO_1\[22\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Info: Pin GPIO_1\[23\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Info: Pin GPIO_1\[24\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Info: Pin GPIO_1\[25\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Info: Pin GPIO_1\[26\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Info: Pin GPIO_1\[27\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Info: Pin GPIO_1\[28\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Info: Pin GPIO_1\[29\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Info: Pin GPIO_1\[30\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Info: Pin GPIO_1\[31\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Info: Pin GPIO_1\[32\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently disabled " "Info: Pin GPIO_1\[33\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[34\] a permanently disabled " "Info: Pin GPIO_1\[34\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[35\] a permanently disabled " "Info: Pin GPIO_1\[35\] has a permanently disabled output enable" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! output enable" 0 0}  } {  } 0 0 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "265 " "Warning: Following 265 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[0\] GND " "Info: Pin HEX0\[0\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 181 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX0\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX0[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[1\] GND " "Info: Pin HEX0\[1\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 181 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX0\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX0[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX0[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[2\] GND " "Info: Pin HEX0\[2\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 181 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX0\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX0[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX0[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[3\] GND " "Info: Pin HEX0\[3\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 181 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX0\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX0[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX0[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[4\] GND " "Info: Pin HEX0\[4\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 181 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX0\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX0[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX0[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[5\] GND " "Info: Pin HEX0\[5\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 181 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX0\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX0[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX0[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX0\[6\] GND " "Info: Pin HEX0\[6\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 181 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX0\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX0[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX0[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[0\] GND " "Info: Pin HEX1\[0\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 182 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX1\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX1[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[1\] GND " "Info: Pin HEX1\[1\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 182 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX1\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX1[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[2\] GND " "Info: Pin HEX1\[2\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 182 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX1\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX1[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX1[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[3\] GND " "Info: Pin HEX1\[3\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 182 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX1\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX1[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[4\] GND " "Info: Pin HEX1\[4\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 182 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX1\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX1[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX1[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[5\] GND " "Info: Pin HEX1\[5\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 182 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX1\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX1[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX1\[6\] GND " "Info: Pin HEX1\[6\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 182 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX1\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX1[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX1[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[0\] GND " "Info: Pin HEX2\[0\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 183 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX2\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX2[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[1\] GND " "Info: Pin HEX2\[1\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 183 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX2\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX2[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX2[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[2\] GND " "Info: Pin HEX2\[2\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 183 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX2\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX2[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX2[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[3\] GND " "Info: Pin HEX2\[3\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 183 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX2\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX2[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[4\] GND " "Info: Pin HEX2\[4\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 183 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX2\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX2[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX2[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[5\] GND " "Info: Pin HEX2\[5\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 183 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX2\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX2[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX2[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX2\[6\] GND " "Info: Pin HEX2\[6\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 183 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX2\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX2[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX2[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[0\] GND " "Info: Pin HEX3\[0\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 184 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX3\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX3[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX3[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[1\] GND " "Info: Pin HEX3\[1\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 184 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX3\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX3[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX3[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[2\] GND " "Info: Pin HEX3\[2\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 184 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX3\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX3[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX3[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[3\] GND " "Info: Pin HEX3\[3\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 184 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX3\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX3[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX3[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[4\] GND " "Info: Pin HEX3\[4\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 184 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX3\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX3[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX3[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[5\] GND " "Info: Pin HEX3\[5\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 184 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX3\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX3[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX3[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX3\[6\] GND " "Info: Pin HEX3\[6\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 184 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX3\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX3[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX3[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX4\[0\] GND " "Info: Pin HEX4\[0\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 185 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX4\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX4[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX4[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX4\[1\] GND " "Info: Pin HEX4\[1\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 185 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX4\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX4[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX4[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX4\[2\] GND " "Info: Pin HEX4\[2\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 185 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX4\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX4[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX4[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX4\[3\] GND " "Info: Pin HEX4\[3\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 185 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX4\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX4[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX4[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX4\[4\] GND " "Info: Pin HEX4\[4\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 185 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX4\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX4[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX4[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX4\[5\] GND " "Info: Pin HEX4\[5\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 185 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX4\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX4[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX4[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX4\[6\] GND " "Info: Pin HEX4\[6\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 185 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX4\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX4[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX4[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX5\[0\] GND " "Info: Pin HEX5\[0\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 186 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX5\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX5[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX5[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX5\[1\] GND " "Info: Pin HEX5\[1\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 186 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX5\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX5[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX5[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX5\[2\] GND " "Info: Pin HEX5\[2\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 186 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX5\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX5[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX5[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX5\[3\] GND " "Info: Pin HEX5\[3\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 186 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX5\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX5[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX5[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX5\[4\] GND " "Info: Pin HEX5\[4\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 186 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX5\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX5[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX5[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX5\[5\] GND " "Info: Pin HEX5\[5\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 186 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX5\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX5[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX5[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX5\[6\] GND " "Info: Pin HEX5\[6\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 186 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX5\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX5[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX5[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX6\[0\] GND " "Info: Pin HEX6\[0\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 187 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX6\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX6[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX6[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX6\[1\] GND " "Info: Pin HEX6\[1\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 187 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX6\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX6[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX6[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX6\[2\] GND " "Info: Pin HEX6\[2\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 187 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX6\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX6[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX6[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX6\[3\] GND " "Info: Pin HEX6\[3\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 187 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX6\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX6[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX6[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX6\[4\] GND " "Info: Pin HEX6\[4\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 187 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX6\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX6[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX6[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX6\[5\] GND " "Info: Pin HEX6\[5\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 187 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX6\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX6[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX6[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX6\[6\] GND " "Info: Pin HEX6\[6\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 187 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX6\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX6[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX6[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX7\[0\] GND " "Info: Pin HEX7\[0\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 188 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX7\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX7[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX7[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX7\[1\] GND " "Info: Pin HEX7\[1\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 188 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX7\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX7[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX7[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX7\[2\] GND " "Info: Pin HEX7\[2\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 188 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX7\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX7[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX7[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX7\[3\] GND " "Info: Pin HEX7\[3\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 188 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX7\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX7[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX7[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX7\[4\] GND " "Info: Pin HEX7\[4\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 188 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX7\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX7[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX7[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX7\[5\] GND " "Info: Pin HEX7\[5\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 188 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX7\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX7[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX7[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "HEX7\[6\] GND " "Info: Pin HEX7\[6\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 188 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "HEX7\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX7[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { HEX7[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[0\] GND " "Info: Pin LEDG\[0\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 190 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDG\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[1\] GND " "Info: Pin LEDG\[1\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 190 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDG\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[2\] GND " "Info: Pin LEDG\[2\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 190 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDG\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[3\] GND " "Info: Pin LEDG\[3\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 190 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDG\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[4\] GND " "Info: Pin LEDG\[4\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 190 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDG\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[5\] GND " "Info: Pin LEDG\[5\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 190 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDG\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[6\] GND " "Info: Pin LEDG\[6\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 190 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDG\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[7\] GND " "Info: Pin LEDG\[7\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 190 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDG\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDG\[8\] GND " "Info: Pin LEDG\[8\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 190 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDG\[8\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDG[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[0\] GND " "Info: Pin LEDR\[0\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[1\] GND " "Info: Pin LEDR\[1\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[2\] GND " "Info: Pin LEDR\[2\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[3\] GND " "Info: Pin LEDR\[3\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[4\] GND " "Info: Pin LEDR\[4\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[5\] GND " "Info: Pin LEDR\[5\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[6\] GND " "Info: Pin LEDR\[6\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[7\] GND " "Info: Pin LEDR\[7\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[8\] GND " "Info: Pin LEDR\[8\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[8\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[9\] GND " "Info: Pin LEDR\[9\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[10\] GND " "Info: Pin LEDR\[10\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[10\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[11\] GND " "Info: Pin LEDR\[11\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[11\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[12\] GND " "Info: Pin LEDR\[12\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[12\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[13\] GND " "Info: Pin LEDR\[13\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[13\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[14\] GND " "Info: Pin LEDR\[14\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[14\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[15\] GND " "Info: Pin LEDR\[15\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[15\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[16\] GND " "Info: Pin LEDR\[16\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[16\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LEDR\[17\] GND " "Info: Pin LEDR\[17\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 191 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LEDR\[17\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LEDR[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "UART_TXD GND " "Info: Pin UART_TXD has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 193 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "UART_TXD" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { UART_TXD } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { UART_TXD } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "IRDA_TXD GND " "Info: Pin IRDA_TXD has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 196 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "IRDA_TXD" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { IRDA_TXD } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { IRDA_TXD } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "DRAM_CKE VCC " "Info: Pin DRAM_CKE has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 210 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_CKE" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_CKE } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_CKE } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "FL_RST_N VCC " "Info: Pin FL_RST_N has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 215 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FL_RST_N" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_RST_N } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_RST_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_ADDR\[0\] GND " "Info: Pin OTG_ADDR\[0\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 228 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_ADDR[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_ADDR[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_ADDR\[1\] GND " "Info: Pin OTG_ADDR\[1\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 228 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_ADDR\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_ADDR[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_ADDR[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_CS_N GND " "Info: Pin OTG_CS_N has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 229 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_CS_N" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_CS_N } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_CS_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_RD_N GND " "Info: Pin OTG_RD_N has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 230 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_RD_N" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_RD_N } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_RD_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_WR_N GND " "Info: Pin OTG_WR_N has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 231 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_WR_N" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_WR_N } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_WR_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_RST_N GND " "Info: Pin OTG_RST_N has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 232 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_RST_N" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_RST_N } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_RST_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_FSPEED VCC " "Info: Pin OTG_FSPEED has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 233 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_FSPEED" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_FSPEED } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_FSPEED } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_LSPEED VCC " "Info: Pin OTG_LSPEED has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 234 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_LSPEED" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_LSPEED } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_LSPEED } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DACK0_N GND " "Info: Pin OTG_DACK0_N has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 239 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DACK0_N" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DACK0_N } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DACK0_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DACK1_N GND " "Info: Pin OTG_DACK1_N has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 240 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DACK1_N" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DACK1_N } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DACK1_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_ON VCC " "Info: Pin LCD_ON has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 243 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_ON" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_ON } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_ON } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_BLON VCC " "Info: Pin LCD_BLON has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 244 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_BLON" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_BLON } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_BLON } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_RW GND " "Info: Pin LCD_RW has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 245 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_RW" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_RW } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_RW } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_EN GND " "Info: Pin LCD_EN has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 246 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_EN" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_EN } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_EN } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_RS GND " "Info: Pin LCD_RS has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 247 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_RS" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_RS } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_RS } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_CLK GND " "Info: Pin SD_CLK has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 252 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SD_CLK" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TDO GND " "Info: Pin TDO has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 263 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "TDO" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TDO } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TDO } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_CLK GND " "Info: Pin VGA_CLK has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 265 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_CLK" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_CLK } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_CLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_HS GND " "Info: Pin VGA_HS has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 266 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_HS" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_HS } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_HS } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_VS GND " "Info: Pin VGA_VS has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 267 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_VS" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_VS } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_VS } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_BLANK GND " "Info: Pin VGA_BLANK has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 268 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_BLANK" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_BLANK } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_BLANK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_SYNC GND " "Info: Pin VGA_SYNC has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 269 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_SYNC" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_SYNC } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_SYNC } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[0\] GND " "Info: Pin VGA_R\[0\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 270 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_R\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[1\] GND " "Info: Pin VGA_R\[1\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 270 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_R\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[2\] GND " "Info: Pin VGA_R\[2\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 270 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_R\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[3\] GND " "Info: Pin VGA_R\[3\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 270 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_R\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[4\] GND " "Info: Pin VGA_R\[4\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 270 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_R\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[5\] GND " "Info: Pin VGA_R\[5\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 270 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_R\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[6\] GND " "Info: Pin VGA_R\[6\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 270 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_R\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[7\] GND " "Info: Pin VGA_R\[7\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 270 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_R\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[8\] GND " "Info: Pin VGA_R\[8\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 270 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_R\[8\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_R\[9\] GND " "Info: Pin VGA_R\[9\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 270 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_R\[9\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_R[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[0\] GND " "Info: Pin VGA_G\[0\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 271 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_G\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[1\] GND " "Info: Pin VGA_G\[1\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 271 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_G\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[2\] GND " "Info: Pin VGA_G\[2\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 271 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_G\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[3\] GND " "Info: Pin VGA_G\[3\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 271 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_G\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[4\] GND " "Info: Pin VGA_G\[4\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 271 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_G\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[5\] GND " "Info: Pin VGA_G\[5\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 271 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_G\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[6\] GND " "Info: Pin VGA_G\[6\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 271 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_G\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[7\] GND " "Info: Pin VGA_G\[7\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 271 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_G\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[8\] GND " "Info: Pin VGA_G\[8\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 271 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_G\[8\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_G\[9\] GND " "Info: Pin VGA_G\[9\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 271 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_G\[9\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_G[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[0\] GND " "Info: Pin VGA_B\[0\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 272 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_B\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[1\] GND " "Info: Pin VGA_B\[1\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 272 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_B\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[2\] GND " "Info: Pin VGA_B\[2\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 272 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_B\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[3\] GND " "Info: Pin VGA_B\[3\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 272 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_B\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[4\] GND " "Info: Pin VGA_B\[4\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 272 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_B\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[5\] GND " "Info: Pin VGA_B\[5\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 272 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_B\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[6\] GND " "Info: Pin VGA_B\[6\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 272 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_B\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[7\] GND " "Info: Pin VGA_B\[7\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 272 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_B\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[8\] GND " "Info: Pin VGA_B\[8\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 272 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_B\[8\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "VGA_B\[9\] GND " "Info: Pin VGA_B\[9\] has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 272 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "VGA_B\[9\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { VGA_B[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_CMD GND " "Info: Pin ENET_CMD has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 275 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_CMD" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_CMD } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_CMD } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_CS_N GND " "Info: Pin ENET_CS_N has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 276 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_CS_N" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_CS_N } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_CS_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_WR_N GND " "Info: Pin ENET_WR_N has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 277 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_WR_N" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_WR_N } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_WR_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_RD_N GND " "Info: Pin ENET_RD_N has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 278 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_RD_N" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_RD_N } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_RD_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_RST_N GND " "Info: Pin ENET_RST_N has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 279 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_RST_N" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_RST_N } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_RST_N } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_CLK GND " "Info: Pin ENET_CLK has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 281 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_CLK" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_CLK } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_CLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_DACDAT GND " "Info: Pin AUD_DACDAT has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 286 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUD_DACDAT } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUD_DACDAT } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_XCK GND " "Info: Pin AUD_XCK has GND driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 288 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUD_XCK } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUD_XCK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TD_RESET VCC " "Info: Pin TD_RESET has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 293 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "TD_RESET" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TD_RESET } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { TD_RESET } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[0\] VCC " "Info: Pin OTG_DATA\[0\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[1\] VCC " "Info: Pin OTG_DATA\[1\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[2\] VCC " "Info: Pin OTG_DATA\[2\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[3\] VCC " "Info: Pin OTG_DATA\[3\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[4\] VCC " "Info: Pin OTG_DATA\[4\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[5\] VCC " "Info: Pin OTG_DATA\[5\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[6\] VCC " "Info: Pin OTG_DATA\[6\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[7\] VCC " "Info: Pin OTG_DATA\[7\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[8\] VCC " "Info: Pin OTG_DATA\[8\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[8\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[9\] VCC " "Info: Pin OTG_DATA\[9\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[9\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[10\] VCC " "Info: Pin OTG_DATA\[10\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[10\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[11\] VCC " "Info: Pin OTG_DATA\[11\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[11\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[12\] VCC " "Info: Pin OTG_DATA\[12\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[12\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[13\] VCC " "Info: Pin OTG_DATA\[13\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[13\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[14\] VCC " "Info: Pin OTG_DATA\[14\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[14\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "OTG_DATA\[15\] VCC " "Info: Pin OTG_DATA\[15\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 227 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "OTG_DATA\[15\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { OTG_DATA[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_DATA\[0\] VCC " "Info: Pin LCD_DATA\[0\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_DATA\[1\] VCC " "Info: Pin LCD_DATA\[1\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_DATA\[2\] VCC " "Info: Pin LCD_DATA\[2\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_DATA\[3\] VCC " "Info: Pin LCD_DATA\[3\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_DATA\[4\] VCC " "Info: Pin LCD_DATA\[4\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_DATA\[5\] VCC " "Info: Pin LCD_DATA\[5\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_DATA\[6\] VCC " "Info: Pin LCD_DATA\[6\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "LCD_DATA\[7\] VCC " "Info: Pin LCD_DATA\[7\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 242 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LCD_DATA\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCD_DATA[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_CMD VCC " "Info: Pin SD_CMD has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 251 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SD_CMD" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[0\] VCC " "Info: Pin ENET_DATA\[0\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[1\] VCC " "Info: Pin ENET_DATA\[1\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[2\] VCC " "Info: Pin ENET_DATA\[2\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[3\] VCC " "Info: Pin ENET_DATA\[3\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[4\] VCC " "Info: Pin ENET_DATA\[4\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[5\] VCC " "Info: Pin ENET_DATA\[5\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[6\] VCC " "Info: Pin ENET_DATA\[6\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[7\] VCC " "Info: Pin ENET_DATA\[7\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[8\] VCC " "Info: Pin ENET_DATA\[8\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[8\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[9\] VCC " "Info: Pin ENET_DATA\[9\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[9\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[10\] VCC " "Info: Pin ENET_DATA\[10\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[10\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[11\] VCC " "Info: Pin ENET_DATA\[11\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[11\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[12\] VCC " "Info: Pin ENET_DATA\[12\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[12\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[13\] VCC " "Info: Pin ENET_DATA\[13\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[13\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[14\] VCC " "Info: Pin ENET_DATA\[14\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[14\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "ENET_DATA\[15\] VCC " "Info: Pin ENET_DATA\[15\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 274 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ENET_DATA\[15\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ENET_DATA[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_BCLK VCC " "Info: Pin AUD_BCLK has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 287 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_DAT VCC " "Info: Pin SD_DAT has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 249 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SD_DAT" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "SD_DAT3 VCC " "Info: Pin SD_DAT3 has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 250 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SD_DAT3" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "AUD_DACLRCK VCC " "Info: Pin AUD_DACLRCK has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 285 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[0\] VCC " "Info: Pin GPIO_0\[0\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[1\] VCC " "Info: Pin GPIO_0\[1\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[2\] VCC " "Info: Pin GPIO_0\[2\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[3\] VCC " "Info: Pin GPIO_0\[3\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[4\] VCC " "Info: Pin GPIO_0\[4\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[5\] VCC " "Info: Pin GPIO_0\[5\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[6\] VCC " "Info: Pin GPIO_0\[6\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[7\] VCC " "Info: Pin GPIO_0\[7\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[8\] VCC " "Info: Pin GPIO_0\[8\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[9\] VCC " "Info: Pin GPIO_0\[9\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[10\] VCC " "Info: Pin GPIO_0\[10\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[11\] VCC " "Info: Pin GPIO_0\[11\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[12\] VCC " "Info: Pin GPIO_0\[12\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[13\] VCC " "Info: Pin GPIO_0\[13\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[14\] VCC " "Info: Pin GPIO_0\[14\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[15\] VCC " "Info: Pin GPIO_0\[15\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[16\] VCC " "Info: Pin GPIO_0\[16\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[17\] VCC " "Info: Pin GPIO_0\[17\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[18\] VCC " "Info: Pin GPIO_0\[18\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[19\] VCC " "Info: Pin GPIO_0\[19\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[20\] VCC " "Info: Pin GPIO_0\[20\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[21\] VCC " "Info: Pin GPIO_0\[21\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[22\] VCC " "Info: Pin GPIO_0\[22\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[23\] VCC " "Info: Pin GPIO_0\[23\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[24\] VCC " "Info: Pin GPIO_0\[24\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[25\] VCC " "Info: Pin GPIO_0\[25\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[26\] VCC " "Info: Pin GPIO_0\[26\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[27\] VCC " "Info: Pin GPIO_0\[27\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[28\] VCC " "Info: Pin GPIO_0\[28\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[29\] VCC " "Info: Pin GPIO_0\[29\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[30\] VCC " "Info: Pin GPIO_0\[30\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[31\] VCC " "Info: Pin GPIO_0\[31\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[32\] VCC " "Info: Pin GPIO_0\[32\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[33\] VCC " "Info: Pin GPIO_0\[33\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[34\] VCC " "Info: Pin GPIO_0\[34\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_0\[35\] VCC " "Info: Pin GPIO_0\[35\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 295 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[0\] VCC " "Info: Pin GPIO_1\[0\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[1\] VCC " "Info: Pin GPIO_1\[1\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[2\] VCC " "Info: Pin GPIO_1\[2\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[3\] VCC " "Info: Pin GPIO_1\[3\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[4\] VCC " "Info: Pin GPIO_1\[4\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[5\] VCC " "Info: Pin GPIO_1\[5\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[6\] VCC " "Info: Pin GPIO_1\[6\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[7\] VCC " "Info: Pin GPIO_1\[7\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[8\] VCC " "Info: Pin GPIO_1\[8\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[9\] VCC " "Info: Pin GPIO_1\[9\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[10\] VCC " "Info: Pin GPIO_1\[10\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[11\] VCC " "Info: Pin GPIO_1\[11\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[12\] VCC " "Info: Pin GPIO_1\[12\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[13\] VCC " "Info: Pin GPIO_1\[13\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[14\] VCC " "Info: Pin GPIO_1\[14\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[15\] VCC " "Info: Pin GPIO_1\[15\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[16\] VCC " "Info: Pin GPIO_1\[16\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[17\] VCC " "Info: Pin GPIO_1\[17\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[18\] VCC " "Info: Pin GPIO_1\[18\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[19\] VCC " "Info: Pin GPIO_1\[19\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[20\] VCC " "Info: Pin GPIO_1\[20\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[21\] VCC " "Info: Pin GPIO_1\[21\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[22\] VCC " "Info: Pin GPIO_1\[22\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[23\] VCC " "Info: Pin GPIO_1\[23\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[24\] VCC " "Info: Pin GPIO_1\[24\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[25\] VCC " "Info: Pin GPIO_1\[25\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[26\] VCC " "Info: Pin GPIO_1\[26\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[27\] VCC " "Info: Pin GPIO_1\[27\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[28\] VCC " "Info: Pin GPIO_1\[28\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[29\] VCC " "Info: Pin GPIO_1\[29\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[30\] VCC " "Info: Pin GPIO_1\[30\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[31\] VCC " "Info: Pin GPIO_1\[31\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[32\] VCC " "Info: Pin GPIO_1\[32\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[33\] VCC " "Info: Pin GPIO_1\[33\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[34\] VCC " "Info: Pin GPIO_1\[34\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "GPIO_1\[35\] VCC " "Info: Pin GPIO_1\[35\] has VCC driving its datain port" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 296 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "system_0:u0\|sdram_0:the_sdram_0\|always5~0 " "Info: Following pins have the same output enable: system_0:u0\|sdram_0:the_sdram_0\|always5~0" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[0\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[0\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[7\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[7\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[14\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[14\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[5\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[5\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[13\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[13\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[4\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[4\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[12\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[12\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[3\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[3\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[11\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[11\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[2\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[2\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[10\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[10\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[1\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[1\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[9\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[9\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[8\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[8\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[15\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[15\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DRAM_DQ\[6\] LVTTL " "Info: Type bidirectional pin DRAM_DQ\[6\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 199 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|in_a_write_cycle~16 " "Info: Following pins have the same output enable: system_0:u0\|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave\|in_a_write_cycle~16" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[0\] LVTTL " "Info: Type bidirectional pin FL_DQ\[0\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 212 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[7\] LVTTL " "Info: Type bidirectional pin FL_DQ\[7\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 212 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[5\] LVTTL " "Info: Type bidirectional pin FL_DQ\[5\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 212 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[4\] LVTTL " "Info: Type bidirectional pin FL_DQ\[4\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 212 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[3\] LVTTL " "Info: Type bidirectional pin FL_DQ\[3\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 212 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[2\] LVTTL " "Info: Type bidirectional pin FL_DQ\[2\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 212 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[1\] LVTTL " "Info: Type bidirectional pin FL_DQ\[1\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 212 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional FL_DQ\[6\] LVTTL " "Info: Type bidirectional pin FL_DQ\[6\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 212 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { FL_DQ[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "system_0:u0\|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0\|sram_0_avalon_slave_0_write_n~28 " "Info: Following pins have the same output enable: system_0:u0\|sram_0_avalon_slave_0_arbitrator:the_sram_0_avalon_slave_0\|sram_0_avalon_slave_0_write_n~28" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[8\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[8\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[8] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[15\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[15\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[15] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[15] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[6\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[6\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[6\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[5\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[5\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[5\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[13\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[13\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[13] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[4\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[4\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[4\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[12\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[12\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[12] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[3\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[3\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[3\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[11\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[11\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[11] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[2\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[2\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[2\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[10\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[10\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[10] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[1\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[1\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[1\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[9\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[9\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[9] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[0\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[0\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[0\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[7\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[7\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[7\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional SRAM_DQ\[14\] LVTTL " "Info: Type bidirectional pin SRAM_DQ\[14\] uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 219 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "I2C_AV_Config:u1\|I2C_Controller:u0\|SDO " "Info: Following pins have the same output enable: I2C_AV_Config:u1\|I2C_Controller:u0\|SDO" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional I2C_SDAT LVTTL " "Info: Type bidirectional pin I2C_SDAT uses the LVTTL I/O standard" {  } { { "DE2_NIOS_DEVICE_LED.v" "" { Text "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.v" 254 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 08 00:55:04 2007 " "Info: Processing ended: Sun Apr 08 00:55:04 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:02:32 " "Info: Elapsed time: 00:02:32" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.fit.smsg " "Info: Generated suppressed messages file C:/csce496/final_project/PROCESSOR/DE2_NIOS_DEVICE_LED.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}
