CSCE 932, Spring 2009: Home Work 2

(Fault Simulation and Test Generation)

Due: In one week

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The purpose of this assignment is to gain a deeper understanding of fault simulation and automatic test generation processes and tools by means of both manual and interactive work.

Consider the smallest ISCAS85 benchmark circuit, c17. A schematic is shown below and a gate-level netlist of the circuit is available online from various sources.

(a) Use Atalanta to obtain a collapsed set of single stuck-at faults for the circuits and a set of three random patterns using your own seed so as to minimize the possibility of obtaining the same set as another student in the class.

(b) Determine the fault coverage of the three random patterns using Hope and report the results.

(c) Now choose a random subset of five faults from the collapsed list you obtained in part (a). Given that one of the five faults is present in the faulty circuit your job is to diagnose the fault using the three random test patterns. Describe the process you would use for the diagnosis. In general, given a set of test patterns for a circuit and a set of faults to be diagnosed, outline at least one approach to diagnosis.

(d) In practice, chip makers need to do failure-mode analysis to identify defects on chips, typically by a manual process which involves stripping a packaged chip to the top metal layer of the bare die and employing high-resolution microscopic methods to look for flaws in the die. This is obviously a very expensive process. You are asked to help the test engineer narrow the places to look for possible defects by producing a small set of suspected single stuck-at fault that might be present in the circuit. Outline your approach and illustrate it using the c17 circuit.

(e) Suppose, you do not know that a fault circuit can only have one of a small set of suspect single stuck-at faults. You are asked to generate test patterns that can reduce the suspect list, ideally, to just one fault. Sketch out your idea for doing this.