CSCE 932, Spring 2009: Home Work 1

(Fault Coverage Analysis)

Due: In one week

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The purpose of this assignment is to gain deeper insight into various models proposed in the literature for estimating the fault coverage required for a given defect level by applying them to test data collected on real chips. We will focus on three fault models:

1. Williams and Brown, IEEE Trans. Computers, Dec. 1981, pp. 987-988.

2. Agrawal, Seth, and Agrawal, Jour. Solid State Circuits, Feb 1982, pp. 57-61.

3. de Sousa and Agrawal, Proc. DATE, 2000, pp. 640-644.

The first paper describes a one-parameter model and the other two describe two-parameter models. For the test data, we will use the ones collected by:

· DELCO for an ignition control chip and

· IBM (bus-interface controller chip) for a SEMATECH research project on evaluating the effectiveness of different fault models (see, Nigh et al., “An experimental study comparing relative effectiveness of functional, scan, IDDQ, and delay-fault testing,”, Proc. VTS, 1997, pp. 459-464).

Copies of the papers and the data sets can be obtained by following the hyperlinks above.

To carry out the assignment, you will need to have access to mathematical software, such as MATLAB, which includes programs to do non-linear curve fitting. You may follow the method described in Section 4 of the third paper.

Provide a summary and analysis of your explorations in the form of a technical report of c. 5 pages, including tables, charts, and references.