CSCE 230, Fall 2009

Homework 3 (Appendix C)

Due: Wednesday, 9/23/2009 before class (by Web Handin or hard copy)

Problem 1. [20%]
(a) Write a Boolean expression for the output Z of the above circuit and simplify it as much you can, using the rules of Boolean algebra. Show and justify all steps.

(b) Complete the  truth table for the output Z and write both SOP and POS expressions for it.

Problem 2. [20%] In this problem you are asked to provide proofs using Boolean algebraic identities (see page C-6 of the textbook). 

(a) The 1-bit ALU of Figure C.5.8 shows one way to derive the lower input of the full adder from inputs b and BInvert using an inverter and a 2-input multiplexor. Prove that this logic is functionally equivalent to an exclusive-or gates with  b and BInvert as inputs. (Note that your proof should be entirely symbolic, using Boolean algebaric identities).

(b) Prove that:

abe + cde' +abcd = abe + cde' 

(Note: This is an example of the Consensus Theorem, which says that the consensus term, obtained by eliminating a single opposing literals in two product terms and Anding the remaining literals, is redundant in an expression and can be dropped).

(c) Prove that the dual of the two-input exclusive-or function is its complement but the sum and carry functions of a full adder are self-duals.

Problem 3. [20%] Show the results of adding/subtracting the following pairs of six-bit (i.e. one sign bit and five data bits) two’s complement numbers and indicate whether or not overflow/underflow occurs for
each case:

Problem 4. [20%]

Complete the following timing diagram for the true output Q of the SR-latch, D-latch, +ve-edge-triggered D FF, and -ve-edge-triggered D FF. For the last three cases assume C to be either the control or the clock signal and D to be the data input.

C D S R SR-Latch Q D-Latch Q +ve-edge-triggered Q -ve-edge-triggered Q

Problem 5. [20%] Show the schematic of a SR-latch implemented using 2-input Nand gates.  Correctly mark the latch inputs and outputs and show a state-table description of the Nand latch, indicating the invalid input combination.  Next, construct a D-latch from the Nand latch, using only two-input Nands and argue why your implementation is correct.