Homework - Chapter 5 & Appendix C      Name _____________________________
CSCE 230 Computer Organization
Due Monday, April 9, 2007

Relevant figures:

5.28     Datapath for multicycle
5.37     Finite state machine (also C.3.1)
5.39     Datapath with exceptions
5.40     Finite state machine with exceptions
C.3.9    PLA internals
C.4.2    Address select logic
C.4.3    Dispatch ROM contents

1a. Suppose a shift instruction is to added.  The shifter unit is
    capable of doing single logical shifts either right or left, and
    the direction is controlled by a control line (1 -> right, 0 -> left).
    There is a built-in register for the data being shifted which can be 
    loaded externally or from the shifted data by a second control line
    (1 -> load external, 0 -> shift).  There is also a clock line.

    Incorporate this shifter unit into the multicycle data path so that
    the MIPS sll and srl (with a shift count) can be performed.  You 
    may need to add other components, such as a counter and mux's.

    sll and srl op code: 0 (it's type R!)
    sll function code:  00
    srl function code:  02
    For both commands, register rd receives the shifted value from
       register rs, the amount given by shamt.

    31-26 25-21 20-16 15-11 10-6  5-0
      op    rs    rt    rd  shamt funct


 b. Modify the finite state machine to handle the new shift instructions.
    Hint:  Is there a loop?


 c. Modify the PLA to handle the new shift instructions.  You may
    modify either the original PLA with the next state output built
    in, or the revised PLA with external next state control for a
    few bonus points (assuming you present a good design).


2.  Suppose some instructions were 8 bytes instead of 4 and the data
    path from memory allowed 8 byte transfers, perhaps into a combination
    of the Instruction Register and the Memory Data Register or other
    supplementary register (so that fetch does not require two reads).
    You can assume that the second 4 bytes of an 8 byte instruction
    will always represent an address or immediate data.  Discuss how
    you might modify the data path to take advantage of (in the case
    of 4 byte instructions) fetching two instructions at once.  
    Consider the case of fetching a 4 byte instruction which is
    immediately followed by an 8 byte instruction (of which only the
    first half is fetched.)


3.  Consider the finite state machine and data path for exceptions.
    Modify them to accommodate an external interrupt as follows:
    Add an interrupt flag bit (flip-flop) that is set directly by the 
    interrupting device and can be seen by the Control Unit.  If this 
    bit is set at the end of any instruction and there is no other 
    exception, do the same kind of stuff as you see in state 10 and 
    11, clear the flag bit, and jump to address 8000 0200.


4.  Add the instruction rfe (return from exception) to the datapath.
    A primary task of the rfe instruction is to copy the contents of the
    EPC to the PC.  Add any necessary datapaths and control signals and
    show the necessary modifications to the finite state machine and PLA.


5.  Determine the size of the PLAs needed to implement the multicycle
    machine of section 5.5 assuming that the next-state function is
    implemented with a counter.  Implement the dispatch tables of
    Figure C.5.2 using two PLAs, and the contents of the main control
    unit of Figure C.4.5 using another PLA.  How does the total size
    of this solution compare to the single PLA solution with the next
    state encoded?  What if the main PLAs for both approaches are split
    into two separate PLAs by factoring out the next state or address
    select signals?