CSCE 230 Chapter 5 Exam
Lucky Friday, April 13, 2007         NAME _______________________________

1. a) What are two good clues for dtermining if a datapath takes one
      clock cycle or multiple clock cycles per machine instruction?





   b) Why wasn't there a finite state machine for the single cycle
      implementation in the text?  (Were the authors leaving it out
      so it could be an exercise, or is there something more fundamental?)





2. Imagine state 0 was relabelled as state f and there are no other
   changes in the data path or finite state machine.

   a) Modify the (original with NS lines) PLA to reflect this change.

   b) Modify the (revised with Addr Cntl lines) PLA to reflect this
      change OR explain why this can't be done without also modifying
      the address logic (external to the PLA).




3. Let state 0 be associated with clock number 0.  Then what clock
   numbers are associated with the remaining states?
 
   state  clock  state  clock  state  clock
   1)            4)            7)
   2)            5)            8)
   3)            6)            9)

4. Assume that instead of BEQ we have BNE (with the same op code).
   Which of the following need to be changed?  Show the change.

   a) Data path with control lines

   b) Finite state machine

   c) PLA (in the control unit)


5. Repeat exercise 4. assuming we have BNE (with op code 05) in
   addition to having BEQ.

   a) Data path with control lines

   b) Finite state machine

   c) PLA (in the control unit)


6. Consider the MUX that leads to the PC.  At which clock number are
   the following values available?

   a) Option 0 (the current PC + 4)

   b) Option 1 (the branch address)

   c) Option 2 (the jump address)


7. Add the JAL command (with op code 03).  Note this is very similar
   to a simple jump.  It stores the next PC in register 31.