CSCE432/832 High Performance Processor Architectures
Fall 2009

Classroom: 112 Schorr Center; Time: 9:10am-10:25am, M.W.



Instrutor:  Hong Jiang
    jiang@cse.unl.edu
    472-6747
    Office: 103 Schorr Center, Office Hours (tentative): 10:30-11:30 AM, M.W. (Contact me to setup appointments at other times, if this does not work for you)

TA: T.B.A. 
   
Pre-requisites: CSCE 430, MATH 314, and MATH 380 or ELEC 410; or permission.

 

Prerequisites by Topic:

  1. Mastery of: the principles of classical single-processor Computer Architectures, including:
    1. Memory hierarchies, esp. Cache & main memory,
    2. Scalar processor architecture, RISC vs. CISC philosophies, & scalar pipeline performance.
  2. Familiarity with: Probability, & stochastic performance modeling of scalar processors, given standard stochastic & timing parameters (e.g. hit ratios, access times, cycle times, CPI, branch probabilities).

Course Objectives:

  1. Mastery of: the principles and practice of high-performance processor architectures, including: 
    1. Data parallelism vs. Instruction Level.Parallelism (ILP),
    2. Principles and practice of Superscalar Architectures,
    3. Principles and practice of Very Long Instruction Word (VLIW) Architectures, and
    4. Principles and practice of Multicore (or Chip Multiprocessor, CMP) Architectures.

Required Text:

John P. Shen and Mikko H. Lipasti, Modern Processor Design - Fundamentals of Superscalar Processors, McGraw-Hill Higher Education, 2005.

 

Reference Text & Materials:

John L. Hennessy and David A. Patterson, Computer Architecture -- A Quantitative Approach, 4th Edition, Morgan Kaufmann Publishers Inc., 2007; and

Latest literature from premier research publication venues in the area.

 

Electronic Communication:

Class web page: http://cse.unl.edu/~jiang/cse432/
Class email list: csce432 (to be confirmed)

 

Course Coverage:

            An overview and tentative coverage of the course is listed below:

Main Topics to Be Covered

Readings Required

Lecture Time

Scalar Processor Design

Chapters 1 & 2

2 weeks

Superscalar Organization

Chapter 3

1-2 weeks

Superscalar Techniques & Cases

Chapter 4-7

3-4 weeks

Multicore Processors

References provided

4-5 weeks (possible presentations of latest literature by student teams)

Advanced Techniques for Multicore

Chapters 8-9 + Ref. book + Ref. papers

4-5 weeks (possible presentations of latest literature by student teams)

 

Grading Policy:

•       Pre-requisite exam will be given on the Monday of the second week.

•       One Exam will be given during the course.

•       Course Project dealing with aspects of design and analysis of multicore processor architectures

•       3-4 homework assignments will be given. Each is due in class on its specified due date. Late work is penalized 20% per day. Once solutions are published, late work cannot be accepted for credit.

•       While collaboration on homework is permitted, blatant copying will not be tolerated. Violators, if caught, will subject to penalties ranging from a zero for the homework assignment in question to an F grade for the course, depending on the severity of the violation.

•       Final Grade will be generated according to the weight associated with each component listed below:                  

1.                                  Pre-requisite Test:           6%;  

2.                                  Homework Assignment:    24%; 

3.                                  Exam:                             35%; 

4.                                   Course Project:               35%;

Course Homepage: Please check the course homepage regularly for homework assignments, lecture schedule and notes, and other announcements.