CSCE430/830 Computer Architecture
|
Instrutor: Hong Jiang
jiang@cse.unl.edu
472-6747
Office: 214 Schorr Center
Co-Instructor: Lei Tian,
leitian.hust@gmail.com
Office: 203 Schorr Center
Office Hours: 2:30PM-3:30 PM, M.W.F. 214/203 Schorr
Center (Contact me to setup appointments at other times, if this does not work
for you)
Pre-requisites: CSCE 230, 230L, 310 (Coreq: Math 380 or EE 410) or permission.
Prerequisites by Topic:
1. Mastery
of: Boolean algebra, logic equations, binary numbers (including negatives),
fixed-point binary arithmetic, hexadecimal notation, powers-of-2, logarithms,
exponential numbers.
2. Familiarity with: computer organization, including: logic gates & diagrams, processor organization & operation, memory devices & hierarchies, I/O devices & processes,
3. Familiarity with: at least 1 assembler language, 1 high-level language, 1 graphical process representation (e.g. flow charts), basic data structures, basic logic design, simple datapaths implementation, basic pipelining principles, basic O.S. principles and functions.
4. Exposure to: Basic probability (esp. calculating arithmetic and geometric mean values).
1. Mastery
of: the elements, structures, processes, design trade-offs, & performance
issues of classical single-processor Computer Architectures, including:
a. Scalar and superscalar processor architecture: their relationships to the hardware/software interface, quantitative approaches to the performance evaluation at different levels, competing design philosophies (e.g. five ISA classes, branch prediction schemes), the theory & practice of pipelining, superscalar, speculation, hands-on experience in the design and implementation of pipelined RISC based processor.
b. n-level memory hierarchies (n>2): incl. Cache(s), main memory, virtual memory,
c. I/O: disk drives, buses, redundant and inexpensive array, reliability/availability measurement.
2. Mastery
of: stochastic performance model derivation & evaluation, given
standard stochastic & timing parameters (e.g. access times, CPI, hit
ratios, memory stall times, I/O throughput).
John
L. Hennessy and David A. Patterson, Computer
Architecture -- A Quantitative Approach, 5th Edition, Morgan Kaufmann
Publications, Elsevier, Inc., 2012.
Electronic
Communication:
Course Schedule:
An overview and tentative (and
approximate) schedule of the course is listed below:
|
Main
Topics to Be Covered |
|
Lecture
Time |
|
Fundamentals
of Quantitative Design & Analysis |
Chapter
1: 1.1-1.13 |
1.5-2
weeks |
|
Memory
Hierarchy Design |
Selected
Sections in Chapters 2 & Appendix B |
4-5
weeks |
|
Instruction-Level
Parallelism and Its exploitation |
Selected
Sections in Chapters 3 & Appendix C |
4-5
weeks |
|
Data-Level
Parallelism in Vector, SIMD, and GPU Architectures |
Selected
Sections in Chapters 4 & other online materials |
4-5
weeks |
|
Others:
exams; |
As
needed |
1
week |
Grading Policy:
• 2 equally weighted exams will be given at
around the seventh and fourteenth week respectively.
• A term project will be required in lieu of
the final exam—a semester-long team project—with details to be announced.
• 5-6 homework assignments will be given.
Each is due in class on its specified due date. Late work is penalized 20% per
day until the following Friday.
•
While collaboration on homework is permitted,
blatant copying will not be tolerated. Violators, if caught, will subject to
penalties ranging from a zero for the homework assignment in question to an F
grade for the course, depending on the severity of the violation.
•
Final Grade will be generated according to
the weight associated with each component listed below:
Homework
Assignment: 30%;
Exam
1: 25%;
Exam
2: 25%
Term
Project: 20%;