CSE 230 Lab

Class Links

Syllabus

Office Hours

• David
• Tuesday 1:00-2:00, SRC
• Tuesday 4:00-5:00, SRC
• Dan
• Tuesday 11:30-1:30, Avery 15A
• Thursday 11:30-1:30, Avery 15A

Project Documents

• Project Overview
• First Milestone
• Second Milestone
• Processor Design Files
• Third Milestone (docx)
• Third Milestone (pdf)
• Fourth Milestone (pdf)
• Bonus Milestone (pdf)

Lab Materials

• Week 1, Due 8-27-09
• Lab 1: Introduction to Quartus [Handout]


• Week 2, Due 9-3-09
• Lab 2: Abstraction
• Updated PreLab
• Full Lab
• Quartus Archive
• VHDL Sample
• Bus Example


• Week 3, Due 9-10-09
• Lab 3: Basic ALU
• Prelab & Lab


• Week 4, Due 9-17-09
• Lab 4: Sequential Logic
• Prelab & Lab


• Week 5, Due 10-1-09
• Lab 5: Controller Design
• Prelab & Lab
• Multiplier Datapath
• Updated Multiplier


• Lab 6, Due 10-8-09
• Lab 6: Register Files and SRAM
• Prelab & Lab


• Lab 7, Due 10-15-09
• Lab 7: MIPS
• Prelab & Lab (docx)
• Prelab & Lab (pdf)
• ASM File


• Lab 8, Due 10-22-09
• Lab 8: Introduction to MIPS Programming
• Prelab & Lab (docx)
• Prelab & Lab (pdf)


• Lab 9, Due 10-30-09
• Lab 9: Procedures
• Prelab & Lab (docx)
• FindMin ASM
• BubbleSort ASM


• Lab 10, Due 11-5-09
• Lab 10: Recursion
• Prelab & Lab (pdf)