CSCE 932: Fault Tolerance

Lecture Schedule

Date

Topics

Assignments

1/9

Syllabus and course overview

1/11

Basics of Testing

For Practice-1

1/18

Yield Analysis and Product Quality

Homework 1

1/25,30 & 2/2

(Sub: Jian Kang) Intro to ATPG tools and Fault Simulation

2/6

Fault Coverage Analysis

2/8

Test Generation for Combinational and Sequential Logic

2/15

Homework 2

2/22

Delay testing

2/27

Discussion of Project 1; delay testing

Homework 3

3/3

I have updated and added on to Homework 3 on joint distribution - use the link to the right to access it. The due date is extended to Monday, March 12, midnight. Please submit by email.

Homework 3 Updated

3/6

Updated Homework 3; Project 2; delay testing

3/8

Project 3 (Powerpoint of ITC-03 presentation on DTS); delay testing

3/22

Fault Diagnosis

3/29

RTL Test Generation (References: (1) L. Lingappan, et al., VLSI Design 2007 and (2) M. C. Hansen and J. P. Hayes, VTS 1995)

4/5

High-Level Fault Grading (References: (1) Mao & Gulati, ITC96 (2) Thaker, Agrawal, & Zaghloul. (VTS99 and ITC2000)

4/10

Scheduling of presentations on RTL and SoC testing (Let me know the topic by the end of this week), Intro. to SoC testing and IEEE 1500 standard

Homewor 4

4/12

SoC Wrapper/TAM Design (References: (1) Aerts and Marinissen, ITC98 and (2) Iyengar et al., JETTA, March 2002)

4/17

On-Chip Networks and Testing -I

4/19

On-Chip Networks and Testing -II

4/24

Class Presentations:
1. Robert Sprick: SoC Test Architecture with RF/Wireless Connectivity (D. Zhao, et al. ETS'05)
2. Yuyan Xue: Modular SOC Testing With Reduced Wrapper Count (Q. Xu and N. Nicolici, IEEE TCAD, Dec '05)

4/26

Class Presentation:
3. Xinwang Zhang: Power-aware NOC Reuse on the Testing of Core-based Systems (E. Cota et al., ITC'03)

4/30

1:00-3:00 PM: Project Presentations (Final written reports due by midnight, Thursday, 4/3/2007)

Projects

Fault analysis using joint distribution (I will describe the project in class on 2/27. Here is a related paper by my former student, Hailong Cui)

Path sensitization analysis using symbolic backtrace (I will discuss the project in class on 3/6 and provide related handouts)

A new low-power scan-path architecture using double-tree scan (I will discuss the project in class on 3/8 and provide related handouts). A related paper with my former student, Sheng Zhang, and Prof. B. B. Bhattacharya.

Web Links

Starting References For:

RTL test generation and testability analysis:

[1] L. Lingappan, S. Ravi, and N. K. Jha, "Satisfiability-based test generation for nonseparable RTL controller-datapath circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25(3) pp. 544-557.

[2] S. Boubezari, E. Cerny, B. Kaminska, and B. Nadeau-Dostie, "Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18(9) pp. 1327-1340, September 1999.

[3] I. Ghosh, N. K. Jha, and S. Bhawmik, "A BIST scheme for RTL circuits based on symbolic testability analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19(1) pp. 111-128.

[4] L. Lingappan, V. Gangaram, and N. K. Jha, "Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits," in Proc. 20th International Conference on VLSI Design pp. 504-512, 2007.

[5] J. Kang, S. C. Seth, and V. Gangaram, "Efficient RTL Coverage Metric for Functional Test Selection," VTS 2007 (to be presented)

[6] W. Mao and R. K. Gulati, "Improving Gate Level Fault Coverage by RTL Fault Grading," ITC 1996, pp. 150-159.

[7] P. A. Thaker, V. D. Agrawal, and M. E. Zaghloul, "Validation vector grade (VVG): a new coverage metric for validation and test," VTS 1999.

[8] C. J. Stolicny et al. "Alpha 21164 Manufacturing Test Development and Coverage Analysis,", IEEE Design and Test, July-September 1998, pp. 98-104.

[9] M. C. Hansen and J. P. Hayes, "High-Level Test Generation using Physically-Induced Faults", VLSI Test Symposium, 1995, pp. 20-28.

[10] M. C. Hansen and J. P. Hayes, "High-Level Test Generation Using Symbolic Scheduling", ITC 1995, pp. 585-595.

SoC Testing:

[1] Chandra, A.; Chakrabarty, K., "A unified approach to reduce SOC test data volume, scan power and testing time,"
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 22 Issue: 3 Mar 2003, Page(s): 352- 363.

[2] Benso, A.; Di Carlo, S.; Prinetto, P.; Zorian, Y., "A hierarchical infrastructure for SoC test management," IEEE Design & Test of Computers, Volume: 20 Issue: 4 July-Aug. 2003, Page(s): 32- 39.

[3] Qiang Xu; Nicolici, N., "Modular SOC testing with reduced wrapper count,"
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Volume: 24 Issue: 12 Dec. 2005, Page(s): 1894- 1908.

[4] Waayers, T.; Marinissen, E.J.; Lousberg, M., "IEEE Std 1500 Compliant Infrastructure for Modular SOC Testing,", 14th AsianTest Symposium, 2005. Page(s): 450- 450

[5] Zorian, Y., "Today's SOC test challenges,"
ITC 2005. Page(s): 2 pp.-

[6] Devanathan, V.R.; Ravikumar, C.P.; Kamakoti, V.
"Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms," VLSI Design, 2007. Page(s): 351-356.

[7] Zhao, D.; Upadhyaya, S.; Margala, M.
"A new SoC test architecture with RF/wireless connectivity," European Test Symposium, Page(s): 14- 19.
ITRS 2005 (The full document has many sections and is quite long. Of particular interest to us in this course are the sections: Executive Summary, System Drivers, Design, Test & Test Equipment, and to some extent, Yield Enhancement)